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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LS7766 датащи(PDF) 9 Page - LSI Computer Systems |
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LS7766 датащи(HTML) 9 Page - LSI Computer Systems |
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9 / 14 page  For VDD = 3.3V ±10% Parameter Symbol Min. Value Max.Value Unit Remarks Quadrature Mode (See Fig. 4 - 6) PCKI High Pulse Width t1 24 - ns - PCKI Low Pulse Width t2 24 - ns - PCKI Frequency fpCK - 20 MHz - Filter Clock (ff) Period t3 50 - ns t3 = t1+ t2, MDR0 <7> = 0 t3 100 - ns t3 = t1+ t2, MDR0 <7> = 1 Filter Clock frequency ff - 20 MHz ff = 1/t3 Quadrature Separation t4 52 - ns t4 > t3 Quadrature Clock Pulse Width t5 105 - ns t5 > 2t3 Quadrature Clock frequency fQA, fQB - 4.5 MHz fQA = fQB < 1/4t3 Quadrature Clock to Count Delay tQ1 4t3 5t3 - - x1, x2, x4 Count Clock Pulse Width tQ2 25 - ns tQ2 = t3/2 Quadrature Clock to FLGa delay tfda 4.5t3 5.5t3 ns - Quadrature Clock to FLGb delay tfdb 3t3 4t3 ns - INDX/ Input Pulse Width tid 60 - ns tid > t4 INDX/ set-up time tis 10 - ns - INDX/ hold time tih 10 - ns - FLGa Output Width tfw 50 - ns tfw ≈ t4 Non-Quadrature Mode (See Fig. 7 - 8) Clock A - High Pulse Width t6 24 - ns - Clock A - Low Pulse Width t7 24 - ns - Direction Input B Set-up Time t8s 24 - ns - Direction Input B Hold Time t8 20 - ns - Clock Frequency fA - 20 MHz fA = (1/(t6 + t7)) Clock to FLGa Out Delay t9 - 40 ns - FLGa Out Pulse Width t10 24 - ns t10 = t7 INDX/ Pulse Width t11 30 - ns - 7766-110806-9 For VDD = 5V ±10% Parameter Symbol Min. Value Max.Value Unit Remarks Quadrature Mode (See Fig. 4 - 6) PCK High Pulse Width t1 12 - ns - PCK Low Pulse Width t2 12 - ns - PCK frequency fpCK - 40 MHz - Filter Clock (ff) period t3 25 - ns t3 = t1+ t2, MDR0 <7> = 0 t3 50 - ns t3 = t1+ t2, MDR0 <7> = 1 Filter Clock frequency ff - 40 MHz - Quadrature Separation t4 26 - ns t4 > t3 Quadrature Clock Pulse Width t5 52 - ns t5 > 2t3 Quadrature Clock frequency fQA, fQB - 9.6 MHz fQA = fQB < 1/4t3 Quadrature Clock to Count Delay tQ1 4t3 5t3 - - x1, x2, x4 Count Clock Pulse Width tQ2 12 - ns tQ2 = t3/2 Quadrature Clock to FLGa delay tfda 4.5t3 5.5t3 ns - Quadrature Clock to FLGb delay tfdb 3t3 4t3 ns - INDX/ Input Pulse Width tid 32 - ns tid > t4 INDX/ set-up time tis 5 - ns - INDX/ hold time tih 5 - ns - FLGa Output Width tfw 24 - ns tfw ≈ t4 Non-Quadrature Mode (See Fig. 7 - 8) Clock A - High Pulse Width t6 12 - ns - Clock A - Low Pulse Width t7 12 - ns - Direction Input B Set-up Time t8 12 - ns - Direction Input B Hold Time t8 10 - ns - Clock frequency fA - 40 MHz fA = (1/(t6 + t7)) Clock to FLGa Out Delay t9 - 20 ns - FLGa Out Pulse Width t10 12 - ns t10 = t7 INDX/ Pulse Width t11 15 - ns - |
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