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ZXLB1600 датащи(PDF) 3 Page - Diodes Incorporated |
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ZXLB1600 датащи(HTML) 3 Page - Diodes Incorporated |
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3 / 16 page ![]() ZXLB1600 ISSUE 3 - SEPTEMBER 2003 3 SEMICO NDUC TORS Symbol Parameter Conditions Min Typ Max Units Output voltage control by dc voltage applied to ‘ADJ’ pin VADJ (nom) Internal reference voltage ‘ADJ’ pin floating, ‘EN’= VIN 1.23 V Temperature coefficient of VADJ 40 ppm/ C VADJ External overdrive voltage range on ‘ADJ’ pin for output voltage control 0.5 V ADJ (NOM) V IADJ Input current into VADJ pin 0.5<VADJ <VADJ (NOM) -10 A VSENSE Default Output voltage ‘ADJ’ pin floating, ‘EN’= VIN 27 29 V Output voltage control by PWM signal applied to ‘EN’ input ∆T/T PWM duty cycle range at ‘EN’ input 10kHz (5) < f < 100kHz, V ENH =VIN 40 100 % fLPF Internal low pass filter cut-off frequency 4 kHz ALPF Filter attenuation f=30kHz 52.5 dB Internal voltage setting resistors for output voltage R1 Ref. Block diagram 317 k R2 6.93 M Enable input VENL Low level Input voltage Device in shutdown 0.4 V VENH High level Input voltage Device active 1.4 Vin V IENL Low level input current VEN =0V -100 nA IENH High level input current VEN =VIN 100 nA TEN(hold) Enable active hold time (6) VEN switched from high to low 120 s Low-battery detection circuit VLBT Detection threshold VIN falling 1.94 2.02 V Temperature coefficient of VBLT 20 ppm/ C VBLHYS Hysteresis VIN rising 20 mV Ref (LBD) Internal reference voltage 1.21 V VLBT (max) Maximum voltage on LBT pin V in-0.5 V IBLOL Low level output current Output ‘on’ 1 mA VBLOL Low level output voltage IBLOL = 0.5mA 0.4 V IBLOH High level output current Output ‘off’ , VBLOH = 29V 2 A VBLOH High level output voltage Output ‘off’ 29 V Internal voltage setting resistors for low-battery detection circuit R3 Ref. block diagram 1.56 M R4 2.44 M ELECTRICAL CHARACTERISTICS (Cont.) Test conditions unless otherwise stated: VIN = 3.0V, TAMB = 25°C Note: 5) This is the minimum PWM frequency to maintain a continuous output. Lower frequencies can be used, but will result in gated operation of the device i.e. device enters shutdown when EN is low (see Note 6). 6) This is the time for which the device remains active after the EN pin has been driven low. This delay allows a continuous output to be maintained during PWM mode operation at frequencies higher than 10kHz. |
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