R2J20751NP

Preliminary

R07DS0240EJ0100 Rev.1.00

Page 9 of 25

Jan 26, 2011

Description of Operation

Peak Current Control

The control IC operates as current programmed control mode, in which output of the converter is controlled by the

choice of the peak current from the high-side MOS FET. The current from this MOS FET is sensed by an active current

sensing circuit (ACS), the output current of which is 1/13700 (50 ppm) of the MOS FET current. The ACS current is

then converted to certain voltage by external resistor on the CS pin. The CS voltage is fed to the internal current sense

comparator via the slope compensation circuit, and then compared with current control signal which determined from

the error amplifier output voltage (EO) via an NPN transistor and resister network.

To start with, the RES pulse from pulse generator resets a latch, then the high-side MOS FET is turned on. The latch

output (Q bar) is toggled when CS voltage reaches the level of the current control signal on EO, the high-side MOS

FET is turned off, and the low-side MOS FET is turned off after a certain dead time interval. The IC remains in this

state until the arrival of the next RES pulse.

Applying current information for the control loop, the converter loop compensation design will be simple.

Maximum Duty-Cycle Limitation

If the current-sense comparator output is not toggled 60-ns prior to the arrival of the next RES pulse, an internal

maximum duty pulse is generated and forces toggling of SR latch. So, the duty cycle of the high-side MOS FET is

limited by the maximum duty period.

The maximum duty period of the high-side MOS FET depends on its switching frequency.

Max. duty = 1 – 60 ns

 Fsw

OCP Hiccup Operation

Eight times the voltage of CS exceeds 1.5 V, OCP hiccup circuit disables switching operation of the IC and MOS FETs.

Internal circuitry also pulls the TRK-SS pin down to SGND. The IC is turned off for a period of 1024 RES pulses; after

this has elapsed, switching operation of the IC is restarted from the soft-start state.

UVLO and ON/OFF Control

When VCIN is under the start-up voltage, it is in the UVLO condition, functioning of the IC is disabled. The oscillator

is turned off, both high and low-side MOS FETs are turned off, and the TRK-SS pin is pulled down. Furthermore, if the

ON/OFF pin is the low state or left open, functioning of the IC is disabled and both MOS FETs are turned off.

Oscillator and Pulse Generator

The frequency of the oscillator (Fct) is set by the value of the external capacitor connected to the CT pin. The switching

frequency (Fsw) is not the same as Fct, which also depends on the phase number N. The following equations determine

these frequencies.

Oscillator frequency: Fct = 160

A / (2  CT(F)  0.8 V)  N (Hz)

Switching frequency: Fsw = Fct / N

(Hz)

In multi-phase operation, connect the CT pins for all devices.