65C datasheet(79/112 Pages) RENESAS

79 / 112 page

R01DS0015EJ0100 Rev.1.00

Page 79 of 109

Feb 07, 2011

M16C/65C Group

5. Electrical Characteristics

VCC1 = VCC2 = 5 V

Switching Characteristics

(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.2.4.3

In 2 or 3 Waits Setting, and When Accessing External Area and Using

Multiplexed Bus

Notes:

Calculated according to the BCLK frequency as follows:

n is 2 for 2-wait setting, 3 for 3-wait setting.

Calculated according to the BCLK frequency as follows:

When using multiplex bus, set f(BCLK) 12.5 MHz or less.

Calculated according to the BCLK frequency as follows:

Table 5.38

Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When

Accessing External Area and Using Multiplexed Bus) (5)

Symbol

Parameter

Measuring

Condition

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address output delay time

See

Figure 5.14

th(BCLK-AD)

Address output hold time (in relation to BCLK)

0ns

th(RD-AD)

Address output hold time (in relation to RD)

(Note 1)

th(WR-AD)

Address output hold time (in relation to WR)

(Note 1)

td(BCLK-CS)

Chip select output delay time

th(BCLK-CS)

Chip select output hold time (in relation to BCLK)

0ns

th(RD-CS)

Chip select output hold time (in relation to RD)

(Note 1)

th(WR-CS)

Chip select output hold time (in relation to WR)

(Note 1)

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

0ns

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

0ns

td(BCLK-DB)

Data output delay time (in relation to BCLK)

td(DB-WR)

Data output delay time (in relation to WR)

(Note 2)

th(WR-DB)

Data output hold time (in relation to WR)

(Note 6)

td(BCLK-ALE)

ALE signal output delay time (in relation to BCLK)

th(BCLK-ALE)

ALE signal output hold time (in relation to BCLK)

−4ns

td(AD-ALE)

ALE signal output delay time (in relation to Address)

(Note 3)

th(AD-ALE)

ALE signal output hold time (in relation to Address)

(Note 4)

td(AD-RD)

RD signal output delay from the end of address

0ns

td(AD-WR)

WR signal output delay from the end of address

0ns

tdz(RD-AD)

Address output floating start time

8ns

0.5

BCLK

()

----------------------10 ns

[]

–

0.5

–

() 10

BCLK

()

------------------------------------40 ns

[]

–

0.5

BCLK

()

----------------------25 ns

[]

–

0.5

BCLK

()

----------------------15 ns

[]

–

0.5

BCLK

()

----------------------20 ns

[]

–

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