ADP5042 datasheet(21/32 Pages) AD

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ADP5042

Rev. 0 | Page 21 of 32

Watchdog 1 Input

The ADP5042 features a watchdog timer that monitors micro-

processor activity. A timer circuit is cleared with every low-to-

high or high-to-low logic transition on the watchdog input pin

(WDI1), which detects pulses as short as 80 ns. If the timer

counts through the preset watchdog timeout period (tWD1), reset

is asserted. The microprocessor is required to toggle the WDI1

pin to avoid being reset. Failure of the microprocessor to toggle

WDI1 within the timeout period, therefore, indicates a code

execution error, and the reset pulse generated restarts the

microprocessor in a known state.

As well as logic transitions on WDI1, the watchdog timer is also

cleared by a reset assertion due to an undervoltage condition on

the monitored rail. When reset is asserted, the watchdog timer

is cleared and does not begin counting again until reset deasserts.

Watchdog 1 timer can be disabled by leaving WDI1 floating or

by three-stating the WDI1 driver. The pin WMOD controls the

Watchdog 1 operating mode. If WMOD is set to logic level low,

Watchdog 1 is enabled as long as WDI1 is not in three-state. If

WMOD is set to logic level high, Watchdog 1 is always active

and cannot be disabled by a three-state condition. WMOD

input has an internal 200 kΩ pull-down resistor.

Watchdog 1 timeout is factory set to two possible values as

indicated in Table 17.

WDI1

nRSTO

tRP1

tWD1

VSENSED

VTH

Figure 58. Watchdog 1 Timing Diagram

Watchdog 2 Input

The ADP5042 features an additional watchdog timer that

monitors microprocessor activity in parallel to the first watchdog

with a much longer timeout. This provides additional security

and safety in case Watchdog 1 is incorrectly strobed. A timer

circuit is cleared with every low-to-high or high-to-low logic

transition on the watchdog input pin (WDI2), which detects pulses

as short as 8 µs. If the timer counts through the preset watchdog

timeout period (tWD2), reset is asserted, followed by a power

cycle of all regulators . The microprocessor is required to toggle

the WDI2 pin to avoid being reset and powered down. Failure

of the microprocessor to toggle WDI2 within the timeout period,

therefore, indicates a code execution error, and the reset output

nRSTO is forced low for tRP2. Then, all the regulators are turned

off for the tPOFF time. After the tPOFF period, the regulators are re-

activated according to a predefined sequence (see Table 9). Finally,

the reset line (nRSTO) is asserted for tRP1. This guarantees a

clean power-up of the system and proper reset.

As well as logic transitions on WDI2, the watchdog timer is also

cleared by a reset assertion due to an undervoltage condition on

the VTH monitored rail which can be factory programmable

between VOUT1, VOUT2, VOUT3, and AVIN (see Table 20).

When reset is asserted, the watchdog timer is cleared and does

not begin counting again until reset deasserts.

Watchdog 2 timeout is factory set to seven possible values as

indicated in Table 18. One additional option allows Watchdog 2

to be factory disabled.

AVIN/VINx/ENx

VOUT1

VOUT2

VOUT3

nRSTO

WDI2

WSTAT

tPOFF

tRP2

tWD2

tRP1

tWDCLEAR

tD1

tD2

VTH

tD2

Figure 59. Watchdog 2 Timing Diagram (Assuming That VOUT2 Is the Monitored Rail)

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