PCA9525DP datasheet(7/22 Pages) NXP

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PCA9525

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Product data sheet

Rev. 1 — 25 February 2011

7 of 22

NXP Semiconductors

PCA9525

Simple 2-wire bus buffer

9.1 Bidirectional data buffer

The bidirectional data buffer will determine which side has first fallen below Vlock and give

that side of the buffer control over the direction of the buffer. For the purpose of this one

LOW-going pulse, that side now becomes the ‘input’ (be it SDA_IN or SDA_OUT).

When the ‘input’ side falls to near VIL, it will begin to drive the ‘output’ side of the buffer

LOW. It will continue to hold the ‘output’ low until the ‘input’ exceeds VIH at which point the

‘output’ is released and will rise as fast as it is permitted by the load and pull-up to which it

is attached. (Assuming, of course, that the ‘output’ is not otherwise held LOW by some

other device on the bus on that side of the buffer.)

When the ‘input’ side again exceeds Vunlock, it will release its control of the buffer direction.

At this point, if the ‘output’ side was being held LOW (< Vlock) by another device, it will

immediately gain control and now become the ‘input’. What was the ‘input’ will now

become the ‘output’, and the process will repeat as above, but in the opposite direction.

Tamb =25 °C

Fig 5.

Typical input levels versus supply voltage

Fig 6.

Typical VIH − VIL hysteresis versus supply

voltage

Tamb =25 °CIOL =4mA

Fig 7.

Typical LOW-level output voltage versus

pull-up resistance

Fig 8.

Typical LOW-level output voltage versus

ambient temperature

(V)

VDD (V)

002aaf333

Vlock

VIH

VIL

400

600

200

800

1000

VI(hys)

(V)

VDD (V)

002aaf334

Tamb = +85 °C

+25

°C

−40 °C

100

VOL

(mV)

RPU (kΩ)

010

002aaf335

VDD = 5.5 V

2.7 V

100

200

300

VOL

(mV)

Tamb (C)

−50

150

100

050

002aaf336

VDD = 5.5 V

2.7 V

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