PCA9525

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 1 — 25 February 2011

3 of 22

NXP Semiconductors

PCA9525

Simple 2-wire bus buffer

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

Refer to Figure 1 “Block diagram of PCA9525”.

The power supply voltage for the PCA9525 may be any voltage in the range 2.7 V to

5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the ports

is a percentage of the IC’s power supply, hence noise margin considerations should be

taken into account when selecting an operating voltage.

7.2 SCL_IN, SCL_OUT — clock signal inputs/outputs

The clock signal buffer is unidirectional, although the direction may be reversed under

master device generates a unidirectional clock signal to the slave. For lowest cost, the

PCA9525 combines unidirectional buffering of the clock signal with a bidirectional buffer

for the data signal. Clock stretching is therefore not supported and slave devices that may

require clock stretching must be accommodated by the master adopting an appropriate

Fig 2.

Pin configuration for SO8

Fig 3.

Pin configuration for TSSOP8

PCA9525D

EN

SCL_OUT

SDA_OUT

SCL_IN

SDA_IN

DIR

002aaf330

1

2

3

4

6

5

8

7

PCA9525DP

EN

SCL_OUT

SDA_OUT

SCL_IN

SDA_IN

DIR

002aaf331

1

2

3

4

6

5

8

7

Table 2.

Pin description

Symbol

Pin

Description

EN

1

enable

SCL_OUT

2

clock buffer, slave side

SCL_IN

3

clock buffer, master side

4

supply ground

DIR

5

clock direction

SDA_IN

6

data buffer, master side

SDA_OUT

7

data buffer, slave side

8

positive supply