LC651154N datasheet(13/39 Pages) SANYO

13 / 39 page

No. 6278-13/39

LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L

Parameter

Symbol

Conditions

Applicable pins

Ratings

Unit

and notes

min

typ

max

VIL (1)

Output n-channel transistors off VDD = 4 to 6 V

Port

VSS

0.3 VDD

VIL (2)

Output n-channel transistors off VDD = 3 to 6 V

Port

VSS

0.25 VDD

VIL (3)

Output n-channel transistors off VDD = 4 to 6 V

INT, SCK, SI

VSS

0.25 VDD

VIL (4)

Output n-channel transistors off VDD = 3 to 6 V

INT, SCK, SI

VSS

0.2 VDD

Low-level input voltage

VIL (5)

External clock specifications VDD = 4 to 6 V

OSC1

VSS

0.25 VDD

VIL (6)

External clock specifications VDD = 3 to 6 V

OSC1

VSS

0.2 VDD

VIL (7)

VDD = 4 to 6 V

TEST

VSS

0.3 VDD

VIL (8)

VDD = 3 to 6 V

TEST

VSS

0.25 VDD

VIL (9)

VDD = 4 to 6 V

RES

VSS

0.25 VDD

VIL (10)

VDD = 3 to 6 V

RES

VSS

0.2 VDD

The clock may have a

frequency up to 4.33 MHz

Operating frequency

fop (Tcyc)

when either the divide-by-

VDD = 3 to 6 V

200

1444

kHz (µs)

(cycle time)

three or divide-by-four

(20)

(2.77)

internal divider circuit option

is used.

External clock conditions

Figure 1.

Frequency

text

VDD = 3 to 6 V

OSC1

200

4330

kHz

Pulse width

textH, textL

VDD = 3 to 6 V

OSC1

Rise and fall times

textR, textF

VDD = 3 to 6 V

OSC1

Recommended oscillator

circuit constants

Cext

Figure 2

VDD = 3 to 6 V

OSC1, OSC2

270 ±5%

Rext

12 ±1%

Ω

Two-pin RC oscillator

Cext

Figure 2

VDD = 3 to 6 V

OSC1, OSC2

270 ±5%

Rext

5.6 ±1%

Ω

Ceramic oscillator *4

Figure 3

See table 1.

Continued from preceding page.

Either the divide-by-

three or divide-by-four

internal divider circuit

must be used if the

clock frequency

exceeds 1.444 MHz.

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