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CBTL06DP211 датащи(PDF) 6 Page - NXP Semiconductors |
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CBTL06DP211 датащи(HTML) 6 Page - NXP Semiconductors |
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6 / 18 page ![]() CBTL06DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 21 February 2011 6 of 18 NXP Semiconductors CBTL06DP211 DisplayPort Gen1 2 : 1 multiplexer 7. Functional description Refer to Figure 1 “Functional diagram”. The CBTL06DP211 uses a 3.3 V power supply. All main signal paths are implemented using high-bandwidth pass-gate technology and are non-directional. No clock or reset signal is needed for the multiplexer to function. The switch position for the main channels is selected using the select signal GPU_SEL. Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the DDC / AUX channel. The detailed operation is described in Section 7.1. 7.1 Multiplexer/switch select functions The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and DDC_AUX_SEL as described below. DDC_CLK1 H8 differential I/O Pair of single-ended terminals for DDC clock and data signals, path 1, left-side. DDC_DAT1 J8 differential I/O DDC_CLK2 H5 differential I/O Pair of single-ended terminals for DDC clock and data signals, path 2, left-side. DDC_DAT2 J5 differential I/O AUX+ H2 differential I/O High-speed differential pair for AUX or single-ended DDC signals, right-side. AUX − H1 differential I/O HPD_1 J2 single-ended I/O Single ended channel for the HPD signal, path 1, left-side. HPD_2 H3 single-ended I/O Single ended channel for the HPD signal, path 2, left-side. HPDIN J1 single-ended I/O Single ended channel for the HPD signal, right-side. VDD A2, J4 power supply 3.3 V power supply. GND B3, C8, G8, H4, H7 ground Ground. Table 2. Pin description …continued Symbol Ball Type Description Table 3. Multiplexer/switch select control for IN and OUT channels GPU_SEL IN1_n IN2_n 0 active; connected to OUT_n high-impedance 1 high-impedance active; connected to OUT_n Table 4. Multiplexer/switch select control for HPD channel GPU_SEL HPD1 HPD2 0 active; connected to HPDIN high-impedance 1 high-impedance active; connected to HPDIN |
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