No. 6201-13/14

LB1876

7. Hall sensor input signals

Input signals with amplitudes greater than the input circuit hysteresis (42 mV maximum) must be provided to the Hall

inputs. Input amplitudes of over 100 mV are desirable to minimize the influence of noise. If the output waveform is

disturbed by noise (at phase switching), insert capacitors across the input to prevent this.

8. FG input signal

Normally, one of the Hall sensor signals is input as an FG signal. If noise on the FG input is a problem, insert either a

capacitor or a filter consisting of a capacitor and a resistor. Although it is possible to exclude noise from the FG signal

by inserting a capacitor between the FGFIL pin and ground, if this pin's waveform is smoothed excessively, the circuit

may not be able to operate normally. Therefore, if a capacitor is used here, its value must be held to under 2200 pF. If

the position of the capacitor's ground lead is inappropriate, problems due to noise may become more likely to occur.

Select the position carefully.

9. Constraint protection circuit

This IC includes a built-in constraint protection circuit to protect the IC and the motor during motor constraint. In the

start state, when the LD output is high for a fixed period (the unlocked state), the lower side transistor turns off. The

time is set by the capacitor connected to the CSD pin.

Set time (seconds)

≈ 120 × C (µF)

If a 0.068 µF capacitor is used, the protection time will be about 8 seconds. The set time must have a value that

provides an adequate margin relative to the motor start time. The protection circuit does not operate during braking

implemented by switching the clock frequency. Either switch to the stop state or turn off the power and restart to clear

the constraint protection state.

Since the CSD pin also functions as the initial reset pulse generation pin, if connected to ground the logic circuits will

be reset and speed control operation will not be possible. Therefore, if constraint protection is not used, connect CSD to

ground through a resistor of about 220 k

Ω and a capacitor of about 4700 pF in parallel.

10. Phase lock signal

(1) Phase lock range

Since this IC does not have a counter in the speed control system, the speed error range in the phase locked state

cannot be determined solely by the IC's characteristics. (This is because of the influence of the acceleration of the

changes in the FG frequency.) If it is necessary to stipulate this for the motor, it will be necessary to measure this

with the actual motor. Since it is easier for speed errors to occur in the state where the FG acceleration is large, the

largest speed errors are thought to occur during lock pull-in at startup and when unlocked due to clock frequency

switching.

(2) Phase lock signal mask function

When the LDSEL pin is set high or left open, transient lock signals (short low-level periods on the LD output) is

masked. This function masks short low-level periods due to hunting during pull-in and allows a stable lock signal to

be output. However, the lock signal is delayed by amount of masking time.

When the LDSEL pin is set low, transient unlock signals (short high-level periods on the LD output) is masked.

This function prevents short period high-level signals from being output.

The mask time is set with the capacitor connected between the CLD pin and ground.

Mask time (seconds)

≈ 0.9 × C (µF)

A mask time of about 90 ms can be set by using a capacitor of about 0.1 µF. If complete masking is required, the

mask time must be set large enough to provide ample margin. If masking is not required, leave the CLD pin open.