IC Operation Description

1. Speed Control Circuit

This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed

discriminator and the PLL circuit output (using a charge pump technique) an error signal once every two FG periods.

As compared to the earlier technique in which only a speed discriminator circuit was used, the combination of a

speed discriminator and a PLL circuit allows variations in motor speed to be better suppressed when a motor that has

large load variations is used. The FG servo frequency is controlled to be the same frequency as the clock signal input

to the CLK pin. This means that the motor speed can be changed by changing the clock frequency.

2. VCO Circuit

The LB1821M includes an on-chip VCO circuit to generate the reference signal for the speed discriminator circuit.

The reference signal frequency is determined by the following formula.

The range over which the reference signal can be varied is determined by the resistor and capacitor connected to the

R pin (pin 36) and the C pin (pin 37) and by the VCO loop filter constants (the external constants connected to pins

41 and 42).

(Reference Values)

The value of R must not be less than 2.7 k

Ω.

Applications can handle a wider range of speed variations than would be possible if a fixed number of counts was

used by changing the number of discriminator counts (which is related to the divisor in the VCO circuit). The number

of counts can be switched between 64, 128, 256, and 512 by setting the N1 (pin 10) and N2 (pin 11) pins.

3. Output Drive Circuit

To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are

external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with

which the output is on. Since the (external) output switching is handled by the upper side output transistors, a

Schottky diode or similar device must be connected between the output (OUT) and ground. This is because a through

current will flows at the instant the upper side output transistors turn on if a diode with a short reverse recovery time

used for the lower side output transistors. If these transistors have parasitic diode components, then through currents

will occur due to the reverse recovery time of the parasitic diodes despite the inclusion of the external Schottky

diodes.

4. Current Limiter Circuit

detection resistor). The current limitation operation consists of reducing the output duty to suppress the current.

5. Speed Lock Range

The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open

collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to

the speed error to control the motor speed to be within the lock range. Caution is required, since the LD signal may

go on initially at startup. (It will be low while two or three FG signal pulses are input.)

6. Notes on the PWM Frequency

The PWM frequency is determined by the resistor and capacitor connected to the CR pin.

A PWM frequency of between 15 and 25 kHz is desirable. If the PWM frequency is too low, the motor may resonate

No. 5686-8/16

LB1821M

Supply voltage

R (k

Ω)

C (pF)

4.7

390

4.7

820