3

9145D–AUTO–05/10

ATA5021

2.

Pin Configuration

Figure 2-1.

Pinning SO8

5

6

7

8

4

3

2

1

RESET

VDD

GND

OSC

ENA

MODE

TRIG

WUP

Table 2-1.

Pin Description

Pin

Symbol

Function

1WUP

Wake-up input (pull-down resistor)

There is one digitally debounced wake-up input. During the long watchdog window, each signal slope at

the input initiates a reset pulse at pin 5.

2TRG

Trigger input (pull-up resistor)

It is connected to the microprocessor’s trigger signal.

3MODE

Mode input (pull-up resistor)

The processor’s mode signal initiates the switchover between the long and the short watchdog time.

4ENA

Enable output (push-pull)

It is used for the control of peripheral components. It is activated after the processor triggers three times

correctly.

5

RESET

Reset output (open drain)

Resets the processor in the case of under-voltage condition, a wrong trigger event or if a wake-up event

occurs during long watchdog period.

6

VDD

Supply voltage

7

GND

Ground, reference voltage

8

OSC

RC oscillator