FX980 datasheet(41/86 Pages) CMLMICRO

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TETRA Baseband Processor

FX980

D/980/3

TxErrorStatus

Title:

Transmit Error Status register.

Address:

$0x0E

Function:

Description:

This register is the Tx Data path error status register. The TxIrqActive bit is set active when one

of the other bits in this register is the source of an interrupt event. All these error conditions are

caused by transitory events, therefore the error condition is latched (marked with an ‘L’).

Reading this status register causes all latched bits to be set inactive, unless an error event is

currently pending.

Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set

Low) if the source of the interrupt has not been masked in the corresponding Mask register.

Bit

Name

Active State

Function

Reserved. Bit value is not defined.

TxDataPathQOF

High

Data path gain, phase and offset (GPO) adjustment-unit:

Q channel overflow error status bit.

TxDataPathIOF

High

Data path gain, phase and offset (GPO) adjustment-unit:

I channel overflow error status bit.

Tx15tapQOF

High

15-tap Q filter data accumulator overflow error status bit.

Tx15tapIOF

High

15-tap I filter data accumulator overflow error status bit.

Tx49tapOF

High

49-tap I and Q filter data accumulator overflow error status

bit.

Tx79tapOF

High

79-tap I and Q filter data accumulator overflow error status

bit.

TxIrqActive

High

This bit is set High if there is an active interrupt caused by

one of the status bits in this register.

• Address and Data format for TxErrorStatus access

D1 D0

D6 D5 D4 D3 D2

Data field [7:0]

Address field [6:0]

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