10

Function

Power Reading

Ready

Store Command

Complete

Play Command

Complete

Power Register

Pwr

Compand Bits/page

0

1

2

3

4

5

6

7

-39.0 dB

8

10

-36.0

12

14

-33.5

16

18

-30.0

20

22

-28.0

24

32

-25.0

40

48

-22.0

56

64

-19.0

72

80

-16.0

88

128

-10.0

192

256

-6.0

320

384

0dB

448

512

Reading

MSB

Bit 7

1

6

1

5

1

4

3210

0

0000

0

0001

0

0010

0

0011

0

0100

0

0101

0

0110

0

0111

0

1000

0

1001

0

1010

0

1011

0

1100

0

1101

0

1110

0

1111

1

0000

1

0001

1

0010

1

0011

1

0100

1

0101

1

0110

1

0111

1

1000

1

1001

1

1010

1

1011

1

1100

1

1101

1

1110

1

1111

Fig.4 Typical “Power” Readings vs Input Level

Interrupts

An Interrupt Request (IRQ), (if enabled by the Control

Register) is produced by the FX802 to report the following

actions:

Power Reading Ready

Store Command Complete

Play Command Complete.

When an Interrupt Request is produced the Status Register

must be read to ascertain the source of the interrupt. This

action will clear the IRQ output.

Store Command Complete bit

(and an interrupt) is set on completion of a Store command.

This bit is cleared by loading the next Store command, or by

a General Reset command (01

Play Command Complete bit

(and an interrupt) is set on completion of a Play command.

This bit is cleared by loading the next Play command, or by a

General Reset command (01

Power Reading Ready bit

(and an interrupt) is set for every 1024 (1 page) voice-data

bits from the Encoder. This bit is cleared after reading the

Status Register, or by a General Reset command (01

Power Register

The power assessment element shown in Figure 1 assesses

the input signal power for each encoded ‘page’ (every 1024

encoder output bits) by counting the number of 'compand

bits' (000 or 111 sequences in the output bit-stream)

produced during that ‘page,’ shown in Table 6, with typical

encoder input power levels (dB).

Power Reading measurements (Bits 0 – 4) are produced

under the same conditions as in Figure 4.

At the end of each ‘page’ the “Power Reading Ready” bit of

the Status Register is set, an Interrupt Request is generated

(if enabled) and the resulting count converted to a 5-bit

quasi-logarithmic form.

The Power Register reading is interpreted as below.

00000 represents

0 compand bits

00001 represents

1 compand bit

11111 represents

512 compand bits

– the maximum.

This “Power” reading is placed in the Status Register

where it can be read by the

µC.

Figure 4 shows this output in graphical form, indicating the

typical Input Power Level.

5-Bit Power Reading

(Status Register – bits 0 to 4)

0

10

20

30

Average Input ‘Power Level’ (dB )

-50

-40

-30

-20

-10

0dB

5.0

308mVrms

Input Frequency

= 1.0kHz

Sample Clock Rate = 32kb/s

0dB Ref:

= 308mVrms

Table 6 Status Register