5

Controlling Protocol

Control of the functions of the FX802 DVSR Codec is by a group of Address/Commands (A/Cs) and appended instructions or

data to and from the system

µController (see Figure 5). The use and content of these instructions is detailed in the following

paragraphs and tables.

MSB

Byte 1

Byte 0

LSB

15 14 13 12 11 10 9876543210

‘N’

‘X’

Address/Commands

Instruction and data transactions to and from this device

consist of an Address/Command (A/C) byte followed by

either:

(i)

a further instruction or data, or

(ii) a Status or data Reply.

Control and configuration is by writing instructions from the

µController to the Control Register (60

Reporting of FX802 configurations is by reading the Status

Register (61

“C-BUS,” in accordance with the timing information given in

Figures 5 and 6.

A complete list of DBS 800 “C-BUS” Address locations is

published in the System Support Document.

Operation with DRAM

The FX802 can operate with up to 4Mbits of DRAM. When

used with DRAM the DVSR Codec performs four main

functions under the control of commands received over the

“C-BUS” interface from the

µController:

Stores Speech by digitally encoding the analogue input

signal and writing the resulting digital data into the

associated Dynamic RAM (DRAM).

Plays stored speech by reading the digital data stored in the

DRAM and decoding it to provide an analogue output

signal.

Writes data sent over the “C-BUS” from the

µController to

DRAM.

Reads data from DRAM, sending it to the

µC over the

“C-BUS”.

‘Data’ is directed to and from DRAM by the on-chip DRAM

Controller.

Speech

The delta encoder and decoder sampling rates are

independently set, via the Control Register (Table 4), to

(nominally) 16, 25, 32, 50 or 64kbits/s (see Tables 2 and 3),

allowing the user to choose between speech-quality and

storage-time, whilst providing for time-compression or

expansion of the speech signals.

The DVSR Codec can handle from 256kbits to 4Mbits of

DRAM, giving, in the case of 32kbit/s sampling rate, from 8

to 131 seconds of speech storage.

For speech storage purposes, the memory is divided into

'pages' of 1024 bits each, corresponding to 32ms at a

32kbit/s sampling rate.

A 256kbit DRAM contains

256 pages.

A 1Mbit DRAM contains

1024 pages.

4Mbit of DRAM contains

4096 pages.

The Delta Codec may be used without DRAM, when the

decoder sampling rate (8 to 64 kbits/s) is determined by an

external clock source applied to the Decoder Clock pin.

Store and Play Speech Commands

Speech storage and playback may take place

simultaneously.

These commands are transmitted, via “C-BUS,” to the

FX802, in the form:

STORE or PLAY ‘N’ (1024-bit) pages (of encoded

speech data) starting at page ‘X.’

‘N’ is any number from 1 to 16 (pages) and ‘X’ from (page) 0

to 4095 (4Mbit DRAM), as illustrated below.

Preceded by the A/C, this command writes 16-bits (byte 1

(first) and byte 0) of data from the

µC to the FX802 Store or

Play Command Buffer.

Command

Address/Command (A/C) Byte

+

Data

Assignment

Hex.

Binary

Byte/s

MSB

LSB

General Reset

01

0

0

0

00001

Write to Control Register

60

0

1

1

00000

+

2 byte Instruction to Control Register

Read Status Register

61

0

1

1

00001

+

1 byte Reply from Status Register

Store ‘N’ pages. Start page ‘X’

62

0

1

1

00010

+

2 bytes Command – Immediate

Store ‘N’ pages. Start page ‘X’

63

0

1

1

00011

+

2 bytes Command – Buffered

Play ‘N’ pages. Start page ‘X’

64

0

1

1

00100

+

2 bytes Command – Immediate

Play ‘N’ pages. Start page ‘X’

65

0

1

1

00101

+

2 bytes Command – Buffered

Write Data. Start page ‘P’

66

0

1

1

00110

+

2 bytes ‘P’ + Write data

Read Data. Start page ‘P’

67

0

1

1

00111

+

2 bytes ‘P’ + Read data

Write Data – Continue

68

0

1

1

01000

+

Write data

Read Data – Continue

69

0

1

1

01001

+

Read data

Table 1 “C-BUS” Address/Commands