2

2.3 Pin Function Description

XTAL The input of the oscillator inverter.

XTALN The output of the oscillator inverter

CLKIN The input to the internal clock divider circuitry.

When a 3.579545MHz crystal is used, it should be connected across XTAL & XTAL and XTAL

should be directly connected to CLKIN. No other external components are necessary because

the other oscillator components (capacitor, resistor) are on chip.

When an externally available clock signal is used, it should be inserted at CLKIN. XTAL should

be tied to VDD or Vss and XTAL should be left open circuit.

SYSTEM A logic input pin which controls whether the device detects 12Khz SPM tones (logic 1)

or 16Khz SPM tones (logic 0). It has an internal 1 Mohm pull- up resistor (l 2Khz).

NEGIP The negative input, positive input and output respectively of the gain adjusting POSIP

amplifier.

AMPOP

External components are used in conjunction with the op -amp according to the required level

sensitivity and depending on whether the incoming signal is differential or common mode.

VDD The power supply, ground and filter bias pins respectively.

VSS

BIAS Voo and bias should each be de- coupled, via a 1 .0@F capacitor, to VSS.

TTFOP TRUE TONE FOLLOWER OUTPUT. This is the pin that responds and de-

responds within 4ms of a good tone appearing or disappearing.

It is thus like an envelope of the SPM tone.

· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.

DTFOP This is the output of the ‘delayed tone follower’ block.

It will respond when 40ms of good tone has been received within any 48ms window. The 48ms is

divided into 24 ‘packets’ of 2ms each (16Khz mode) or 15 ‘packets’ of 2.667ms each (12Khz

mode). Each packet represents 32 cycles of SPM frequency. The window is a shifting window,

ie. the 48ms window is assessed every 2ms (16Khz mode) or 2.667ms (12Khz). If the necessary

number of good packets are consecutive, the output will respond in the minimum time of 40ms.

· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.

Xtal/Clock:

Xtal/Clock:

Xtal/Clock:

Xtal/Clock:

Xtal/Clock: The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in

conjunction with the Xtal output (see Figure 2); circuit components are on chip. Using this mode

of clock operation, the Clock Out pin should be connected directly to the Clock In pin. If a clock

pulse input is employed to the Clock In pin, this pin must be connected directly to V

Figure 2).

Xtal:

Xtal:

Xtal:

Xtal:

Xtal: The output of the on-chip clock oscillator inverter.

Clock Out:

Clock Out:

Clock Out:

Clock Out:

Clock Out: A clock signal derived from the on-chip Xtal oscillator. If the on-chip oscillator is

used, this pin should be connnected directly to the Clock In pin. This output should not be used

to clock other devices.

Clock In:

Clock In:

Clock In:

Clock In:

Clock In: The 3.579545MHz clock pulse input to the internal clock-dividers. If a clock pulse

input is employed, the Xtal/Clock input (Pin 1) should be connected to V

V

V

V

V

V

BIAS

BIAS

BIAS

BIAS

:::: The output of the on-chip analogue bias circuitry. Held internally at V

be decoupled to V

V

V

V

V

V

SS

SS

SS

SS

:::: Negative supply rail (GND).

Signal In (+):

Signal In (+):

Signal In (+):

Signal In (+):

Signal In (+):

Signal In (-):

Signal In (-):

Signal In (-):

Signal In (-):

Signal In (-):

Amp Out:

Amp Out:

Amp Out:

Amp Out:

Amp Out:

Tone Follower Output:

Tone Follower Output:

Tone Follower Output:

Tone Follower Output:

Tone Follower Output: This output provides a logic “0” (Low) for the period of a detected tone,

Packet Mode Output:

Packet Mode Output:

Packet Mode Output:

Packet Mode Output:

Packet Mode Output: A logic output that will be available after a cumulation of 40ms of 'good'

tone has been received. This packet mode tone follower will only respond when a tone

frequency of sufficient quality has been received for sufficient time, i.e. a cumulation of 40ms in

any 48ms, short tone bursts or breaks will be ignored. This output provides a logic “0” (Low) for

System:

System:

System:

System:

System: The logic input to select device operation to either 12kHz (logic “1” - High) or 16kHz

(logic “0” - Low) SPM systems. This input has an internal 1M

Ω pullup resistor (12kHz).

V

V

V

V

V

DD

DD

DD

DD

:::: Positive supply rail. A single, stable power supply is required. Critical levels and voltages

within the FX631 are dependant upon this supply. This pin should be decoupled to V

SS

by a capacitor mounted close to the pin.

Note that if this device is ‘line’ powered, the resulting supply must be stable. See notes on

Microcircuit Protection from high and spurious line voltages.

No internal connection, leave open circuit.

FX631

FX631

FX631

FX631

FX631

D5

D5

D5

D5

D5

1

1

1

1

1

4

4

4

4

4

5

5

5

5

5

6

6

6

6

6

8

8

8

8

8

12

12

12

12

12

13

13

13

13

13

17

17

17

17

17

18

18

18

18

18

19

19

19

19

19

20

20

20

20

20

21

21

21

21

21

24

24

24

24

24

2, 3, 7,

9, 10,

11, 14,

15, 16,

22, 23

Pin Number

Pin Number

Pin Number

Pin Number

Pin Number

Function

Function

Function

Function

Function

FX631

FX631

FX631

FX631

FX631

DW/P

DW/P

DW/P

DW/P

DW/P

1

1

1

1

1

2

2

2

2

2

3

3

3

3

3

4

4

4

4

4

7

7

7

7

7

8

8

8

8

8

9

9

9

9

9

10

10

10

10

10

11

11

11

11

11

13

13

13

13

13

14

14

14

14

14

15

15

15

15

15

16

16

16

16

16

5, 6,

12

The positive and negative signal inputs to, and the output from, the input gain

adjusting signal amplifier. Refer to the graph in Figure 4 for guidance on

setting level sensitivities to national specifications, and the selection of gain

adjusting components.