Half Duplex GMSK Modem

FX579

© 1996 Consumer Microcircuits Limited

11

D/579/4

Receive Signal Path

The function of the Rx circuitry is to:

a)

Accept an incoming signal from the radio's frequency discriminator at a defined level via

suitable external signal and dc level adjustment

b)

Clean the signal by filtering

c)

Provide dc level thresholds for clock and data extraction

d)

Provide clock timing information for data extraction and external circuits

e)

Provide Rx data as an output in binary form

The output of the radio receiver's frequency discriminator after suitable external signal and level

pin, negative going signal excursions will produce a logic "0".

The signal is then applied to the low pass Rx filter, which has a -3dB corner frequency of 0.56 times the

data bit rate, before being applied to the Level Measuring and Clock and Data Extraction blocks.

Level Measuring Circuit

The 'Level Measuring' block consists of two voltage detectors one of which measures the amplitude of

the 'positive' peaks of the received signal, while the other measures the 'negative' peaks.

These

detectors use the external capacitors connected to the DOC1 and DOC2 pins to form voltage hold or

integrator circuits.

Results of the two measurements are then processed within the modem to establish the optimum dc

level decision thresholds for the Clock and Data Extraction circuits, depending on the received signal

amplitude, BT and any dc offset present.

The receive circuits operate in several control modes as defined by the logic level applied to the

acquire pin. These are explained later - See 'Acquire Sequence'.

Rx Clock Extraction Block

The 'Rx Clock Extraction' circuit is based on a zero crossing tracking loop which uses a multi resolution

digital phase locked loop (PLL). The wide bandwidth mode allows for fast initial phase acquisition.

Eight good zero crossings are required for correct operation.

The highest timing resolution is obtained when the PLL is in its narrow bandwidth mode. This mode of

operation yields the least amount of phase jitter, which is responsible for the associated bit error rate

(BER) performance degradation.

The PLL operating mode is defined by the logic level applied to the ACQUIRE pin - See 'Acquire

Sequence'.

Rx Data Extraction Block

The 'Rx Data Extraction' circuit decides whether each received bit is a "1" or "0" by sampling the

received signal, after filtering, in the middle of each bit period and comparing the sampled voltage

against a threshold derived from the 'Level Measuring' circuit. This threshold is adapted from bit to bit

to compensate for intersymbol interference depending on the chosen BT. The extracted data is output

from the DATAIO pin and should be sampled externally on the rising edge of the received data clock.