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MX839P датащи(PDF) 17 Page - CML Microcircuits |
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MX839P датащи(HTML) 17 Page - CML Microcircuits |
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17 / 20 page ![]() Digitally Controlled Analog I/O Processor 17 MX839 PRELIMINARY INFORMATION © 1998 MX xCOM Inc. www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054 Doc. # 20480164.002 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. Operating Characteristics Notes: 1. Measured over a 0 to 30kHz Band. 2. The extremes of the DAC output range (when resistively loaded) is affected by the output impedance of the DAC buffer. Under these conditions, the output impedance can approach 200 :. However; when the output is operating well within the supply; the output impedance will be significantly lower, thereby improving the loaded performance. 3. RLOAD = 5k: AVDD = 5.0V. 4. Loads less than 1k : will produce output distortion. 5. Small signal impedance, at AVDD = 5V and TAMB = 25°C. 6. Differential non-linearity is defined as the difference in width between adjacent code midpoints and the width of an ideal LSB, divided by the width of an ideal LSB. See Figure 3. 7. Integral non-linearity is defined as the width difference between an actual code midpoint and the line of best fit through all code midpoints, divided by the width of an ideal LSB. See Figure 4. 8. 6MHz operation at VDD = 5.0V only. The ‘C-BUS’ clock must be at lest 4 times slower than the XTAL/CLOCK frequency. Analog Output Digital Input Ideal Response Actual Response Code Width=2LSBs Differential Non-Linearity=1LSB 0V 000$ To $2FF To AVDD Figure 3: Differential Non-Linearity of a D/A Converter 000 040 080 0C0 Analog Output 100 140 180 1C0 200 240 280 2FF 0/768 64/768 128/768 192/768 256/768 320/768 384/768 448/768 512/768 576/768 640/768 704/768 768/768 Digital Input 5 LSBs Ideal Response Actual Response Figure 4: Integral Non-Linearity of a D/A Converter |
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