L9857

Electrical specifications

Doc ID 12896 Rev 2

7/11

2.5

Reset functional diagram

The diagram is guaranteed for the following condition.

Figure 3.

Reset functional diagram

Input-to-output turn-off propogation

delay (50 % input level to 90%

output level)

--

0.1

0.2

μs

RES-to-output turn-off propogation

delay (50% input level to 90%

output levels)

--

0.1

0.3

RES-to-output turn-on propogation

delay (50% input level to 10%

output levels)

--

0.1

0.8

Input characteristics

High logic level input threshold

-

9.5

-

-

V

Low logic level input threshold

-

-

-

6

High logic level input resistance

(Pull-down resistor)

-60

-

300

k

Ω

Low logic level input current

-

-

5

μA

High logic level RES input threshold

Reset signal comes from a

5 V system!

3.5

-

-

V

Low Logic Level RES input

threshold

R eset signal comes from a

5V system!

--

1.4

High logic level RES input

resistance (Pull-down resistor)

Reset signal comes from a

5 V system with pull-up

resistor 3.8 k

60

-

300

k

Ω

Low logic level input current

-

-

5

μA

1.

4 HS-driver reset- inputs and other IC with their input pull-down resistors are connected in parallel with the RESET wire.

The enable input RES- is an active low input, that means a logic low turns the external Power MOSFET off. The input

circuitry has to make sure, that the MOSFET is off, when the pin is open or floating. In the application the RES- pin is tied to

a bipolar open collector transistor or MOSFET open drain transistor with pull-up resistor 3.8K to +5V together with other

RES- inputs of other IC.

Table 6.

Electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

IN

RESET -

HO-VS: -40°C

HO-VS: 25°C

HO-VS: 125°C