NJW1201A

– 6 –

!

CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I

Standard mode

Fast mode

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

UNIT

SCL clock frequency

-

-

100

-

-

400

kHz

Hold time (repeated) START condition.

4.0

-

-

0.6

-

-

µs

Low period of the SCL clock

4.7

-

-

1.3

-

-

µs

High period of the SCL clock

4.0

-

-

0.6

-

-

µs

Set-up time for a repeated START condition

4.7

-

-

0.6

-

-

µs

Data hold time

NOTE)

0

-

-

0

-

-

µs

Data set-up time

250

-

-

100

-

-

ns

Rise time of both SDA and SCL signals

-

-

1000

-

-

300

ns

Fall time of both SDA and SCL signals

-

-

300

-

-

300

ns

Set-up time for STOP condition

4.0

-

-

0.6

-

-

µs

Bus free time between a STOP and START condition

4.7

-

-

1.3

-

-

µs

Capacitive load for each bus line

-

-

400

-

-

400

pF

Noise margin at the Low level

0.5

-

-

0.5

-

-

V

Noise margin at the High level

1

-

-

1

-

-

V

The SDA block in the NJW1201A does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not

providing a hold time of at least 300nsec for the SDA in the master device.

The time-consists of the data-delay-circuit of the SDA terminal are as follows.

(a) Low level $ High level :

(b) High level $ Low level :

In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward

voltage (Vf) as much as possible.

MASTER

SCL

SDA

SBD

NJW1201A