MSC8154 datasheet(53/68 Pages) FREESCALE

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Hardware Design Considerations

MSC8154 Quad-Core Digital Signal Processor Data Sheet, Rev. 2

Freescale Semiconductor

Hardware Design Considerations

The following sections discuss areas to consider when the MSC8154 device is designed into a system.

3.1

Power Supply Ramp-Up Sequence

The following subsections describe the required device initialization sequence.

3.1.1

Clock, Reset, and Supply Coordination

Starting the device requires coordination between several inputs including: clock, reset, and power supplies. Follow this

guidelines when starting up an MSC8154 device:

•

PORESET and TRST must be asserted externally for the duration of the supply ramp-up, using the VDDIO supply.

TRST deassertion does not have to be synchronized with PORESET deassertion. However, TRST must be deasserted

before normal operation begins to ensure correct functionality of the device.

•

CLKIN should toggle at least 32 cycles before PORESET deassertion to guarantee correct device operation. The 32

cycles should only be counted from the time after VDDIO reaches its nominal value (see timing 1 in Figure 33).

•

CLKIN should either be stable low during ramp-up of VDDIO supply (and start its swings after ramp-up) or should

swing within VDDIO range during VDDIO ramp-up, so its amplitude grows as VDDIO grows during ramp-up.

Figure 33 shows a sequence in which VDDIO ramps-up after VDD and CLKIN begins to toggle with the raise of VDDIO supply.

Note:

For details on power-on reset flow and duration, see the Reset chapter in the MSC8154 Reference Manual.

Figure 33. Supply Ramp-Up Sequence with VDD Ramping Before VDDIO and CLKIN Starting With VDDIO

Time

VDDIO Nominal

PORESET/TRST asserted

VDD Nominal

CLKIN starts toggling

VDD applied

PORESET deasserted

VDDIO applied

VDDIO = Nominal

VDD = Nominal

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