MPC8379E datasheet(33/116 Pages) FREESCALE

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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

USB

9.1

USB DC Electrical Characteristics

Table 34 provides the DC electrical characteristics for the ULPI interface at recommended

OVDD = 3.3 V ± 165 mV.

9.2

USB AC Electrical Specifications

Table 35 describes the general timing parameters of the USB interface of the device.

Table 34. USB DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Notes

High-level input voltage

VIH

2OVDD + 0.3

Low-level input voltage

VIL

–0.3

0.8

Input current

IIN

—±30

μA2

High-level output voltage, IOH = –100 μAVOH

OVDD – 0.2

—

Low-level output voltage, IOL = 100 μAVOL

—0.2

—

Note:

1 The minimum V

IL and maximum VIH values are based on the respective minimum and maximum OVIN values found in Table 3.

2 The symbol OV

IN represents the input voltage of the supply and is referenced in Table 3.

Table 35. USB General Timing Parameters (ULPI Mode Only)

Parameter

Symbol 1

Min

Max

Unit

Notes

USB clock cycle time

tUSCK

—

2, 3, 4, 5

Input setup to USB clock—all inputs

tUSIVKH

—

2, 3, 4, 5

Input hold to USB clock—all inputs

tUSIXKH

—

2, 3, 4, 5

USB clock to output valid—all outputs

tUSKHOV

—

2, 3, 4, 5

Output hold from USB clock—all outputs

tUSKHOX

—

2, 3, 4, 5

Note:

1 The symbols for timing specifications follow the pattern of t

(First two letters of functional block)(signal)(state) (reference)(state) for inputs

and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for

the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes

USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold

time.

2 All timings are in reference to the USB clock, USBDR_CLK.

3 All signals are measured from OV

DD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3-V

signaling levels.

4 Input timings are measured at the pin.

5 For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through

the component pin is less than or equal to that of the leakage current specification.

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