MM912F634CV2AP datasheet(74/335 Pages) FREESCALE

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Functional Description and Application Information

Wake-up / Cyclic Sense

MM912F634

Freescale Semiconductor

4.8.2

4.8.2.1

Wake-up Control Register (WCR)

Table 85. Wake-up Control Register (WCR)

Offset(67) 0x12

Access: User read/write

543

210

CSSEL

L5WE

L4WE

L3WE

L2WE

L1WE

L0WE

Reset

111

Note:

67. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 86. WCR - Register Field Descriptions

Field

Description

7-6

CSSEL

Cyclic Sense Select - Configures the HSx output for the cyclic sense event. Note, with no LxWE selected - only the selected

HSx output will be switched periodically, no Lx state change would be detected. For all configurations, the Forced Wake-up

can be activated in parallel in Section 4.8.2.2, “Timing Control Register (TCR)"

00 - Cyclic Sense Off

01 - Cyclic Sense with periodic HS1on

10 - Cyclic Sense with periodic HS2 on

11 - Cyclic Sense with periodic HS1 and HS2 on.

5 - L5WE

Wake-up Input 5 Enabled - L5 Wake-up Select Bit.

0 - L5 Wake-up Disabled

1 - L5 Wake-up Enabled

4 - L4WE

Wake-up Input 4 Enabled - L4 Wake-up Select Bit.

0 - L4 Wake-up Disabled

1 - L4 Wake-up Enabled

3 - L3WE

Wake-up Input 3 Enabled - L3 Wake-up Select Bit.

0 - L3Wake-up Disabled

1 - L3 Wake-up Enabled

2- L2WE

Wake-up Input 2 Enabled - L2 Wake-up Select Bit.

0 - L2 Wake-up Disabled

1 - L2 Wake-up Enabled

1 - L1WE

Wake-up Input 1 Enabled - L1 Wake-up Select Bit.

0 - L1 Wake-up Disabled

1 - L1 Wake-up Enabled

0 - L0WE

Wake-up Input 0 Enabled - L0 Wake-up Select Bit.

0 - L0 Wake-up Disabled

1 - L0 Wake-up Enabled

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