33931 datasheet(8/21 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33931

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 8.0 V

≤ VPWR ≤ 28 V, -40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TIMING CHARACTERISTICS

PWM Frequency(20)

fPWM

–

kHz

Maximum Switching Frequency During Current Limit Regulation(21)

fMAX

–

kHz

Output ON Delay(22)

VPWR = 14 V

tDON

–

μs

Output OFF Delay(22)

VPWR = 14 V

tDOFF

–

μs

ILIM Output Constant-OFF Time(23)

20.5

μs

ILIM Blanking Time(24)

16.5

μs

Disable Delay Time(25)

tDDISABLE

–

8.0

μs

Output Rise and Fall Time(26)

tF, tR

1.5

3.0

8.0

μs

Short-circuit/Over-temperature Turn-OFF (Latch-OFF) Time(27),(28)

tFAULT

–

8.0

μs

Power-ON Delay Time(28)

tPOD

–

1.0

5.0

Output MOSFET Body Diode Reverse Recovery Time(28)

tRR

100

150

Charge Pump Operating Frequency(28)

fCP

–

7.0

–

MHz

Notes

20.

The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to

fully enhance the high side MOSFETs.

21.

The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s

inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM

frequency during current limit.

22.

* Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)

of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of

the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the

output response signal. See Figure 4, page 9.

23.

The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.

24.

The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time

to act.

25.

* Disable Delay Time measurement is defined in Figure 5, page 9.

26.

Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR = 14 V, RLOAD

= 3.0 ohm. See Figure 6, page 9.

27.

Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short-circuit currents

possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short-circuit event detection and

causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode

may cause junction temperatures to rise. Junction temperatures above ~160

°C will cause the output current limit threshold to “fold back”,

or decrease, until ~175

°C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this fold back region

is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).

28.

Parameter is Guaranteed By Design.

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