PCA85232 datasheet(16/54 Pages) NXP

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PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

16 of 54

NXP Semiconductors

PCA85232

LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCA85232 are timed by a frequency

fclk which either is derived from the built-in oscillator frequency fosc:

(6)

or equals an external clock frequency fclk(ext):

(7)

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output

from pin CLK provides the clock signal for cascaded PCA85232 in the system. However,

the clock signal is only available at pin CLK, if the display is enabled. The display is

enabled using the display enable bit (see Table 10).

The output clock frequency is like specified in Table 19 with parameter fclk.

7.5.2 External clock

Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the

external clock input.

7.6 Timing and frame frequency

The timing of the PCA85232 organizes the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs.

In cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between the PCA85232 in the system.

When the internal clock is used, the clock frequency can be programmed by software

such that the frame frequency can be chosen in the range of 117 Hz to 176 Hz (see

Table 16). The internal oscillator is calibrated within an accuracy of

±5.1 % (at

VDD =5.0 V; Tamb =30 °C).

The timing also generates the LCD frame frequency derived from an integer division of fclk

(see Table 16).

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

clk

osc

--------

clk

clk ext

()

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