Datasheet

11

Rev. 1.0, 2009-09-30

SPI Driver for Enhanced Relay Control

SPIDER - TLE7243SL

Input and Power Stages

5

Input and Power Stages

The SPIDER - TLE7243SL is a eight channel low-side relay switch.

The power stages are built by N-channel vertical power MOSFET transistors.

5.1

Power Supply

The SPIDER - TLE7243SL is supplied by two power supply lines

V

The digital power supply line

V

supply

V

There are power-on reset functions implemented for both supply lines. After start-up of the power supply, all SPI

registers are reset to their default values and the device is in stand-by mode. Capacitors at pins

V

V

There is a reset pin available. Low level at this pin causes all registers to be set to their default values and the

quiescent supply currents are minimized.

5.1.1

Limp Home Mode

The SPIDER - TLE7243SL offers the capability of driving dedicated channels during eventual fail-safe operation

of the system. This limp home mode is activated by a high signal at pin LHI. In this mode, the SPI registers are

reset and the input pins are directly routed to their corresponding channels OUT1 to OUT4, see Table 2 for details.

OUT5 to OUT8 are turned off in limp home mode. Furthermore, the SPI is ignored and all input pin are referred to

V

A high signal on LHI overrides a Reset signal on RST. In case of a limp home during standby the device will

therefore wake up and enter the limp home mode.

After limp home operation all registers are reset and the device enters in standby mode following low logic RST

state, or returns to idle (all channels OFF). Next SPI transmission will receive a TER Flag.

Table 2

Routing during limp home mode

5.2

Input Circuit

There are four input pins available at SPIDER - TLE7243SL, which can be configured to be used for control of the

output stages. The INn parameter of the SPI selects the input pin to be used. Figure 4 shows the input circuit of

SPIDER - TLE7243SL.

During Limp home mode a default routing is switched and the SPI commands are ignored.

Input

controlled

Output

IN1

OUT1

IN2

OUT2

IN3

OUT3

IN4

OUT4