TLE5011 datasheet(21/43 Pages) INFINEON

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TLE5011

Specification

Final Data Sheet

V1.1, 2010-05

3.8

Clock Supply (CLK Timing Definition)

The clock signal input “CLK” must fulfill certain requirements described in this section:

•

The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse

width and must be spike filtered.

•

The duty-cycle factor should be 0.5 but can deviate from the values limited by t

CLKh(f_min) and tCLKl(f_min).

•

The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is

generated automatically.

Figure 8

CLK Timing Definition

3.9

Synchronous Serial Communication Interface (SSC)

The 3-pin SSC interface has a bidirectional data line (open drain), a serial clock signal, and Chip Select.

The SSC interface is designed to communicate with a microcontroller with bi-directional SSC interface supporting

open drain. Other microcontrollers may require an external NPN transistor.

This allows communication with SPI-compatible devices.

Table 10

CLK Timing Specification

Parameter

Symbol

Limit Values

Unit

Notes

min.

typ.

max.

Input Frequency

fCLK

3.8

4.00

4.2

MHz

CLK Duty Cycle

1) Minimum duty-cycle factor: t

CLKh(f_min) / tCLK(f_min) with tCLK(f_min) = 1 / fCLK(f_min)

Maximum duty-cycle factor: t

CLKh(f_max) / tCLK(f_min)with tCLKh(f_max) = tCLK(f_min) - tCLKl(min)

CLKDUTY

CLK rise time

tCLKr

from V

L to VH

CLK fall time

tCLKf

from V

H to VL

PLL Frequency

fPLL

100

MHz

fCLK * 25

Digital Clock

fDIG

MHz

( 25 / 4 ) * f

CLK

Digital Clock Periode

tDIG

4 / (25 * f

CLK)

CLKh

CLKl

CLK

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