M48T08 datasheet(9/31 Pages) STMICROELECTRONICS

9 / 31 page

M48T08, M48T08Y, M48T18

Operation modes

Doc ID 2411 Rev 10

9/31

2.1

READ mode

The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip

enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripple-

through access of data from eight of 65,536 locations in the static storage array. Thus, the

unique address specified by the 13 address inputs defines which one of the 8,192 bytes of

data is to be accessed. Valid data will be available at the data I/O pins within address access

time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G

access times are also satisfied. If the E1, E2 and G access times are not met, valid data will

be available after the latter of the chip enable access times (tE1LQV or tE2HQV) or output

enable access time (tGLQV).

The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the

outputs are activated before tAVQV, the data lines will be driven to an indeterminate state

until tAVQV. If the address inputs are changed while E1, E2 and G remain active, output data

will remain valid for output data hold time (tAXQX) but will go indeterminate until the next

address access.

Figure 5.

READ mode AC waveforms

Note:

WRITE enable (W) = high.

AI00962

tAVAV

tAVQV

tAXQX

tE1LQV

tE1LQX

tE1HQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A12

DQ0-DQ7

tE2HQV

tE2HQX

VALID

tE2LQZ

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