MIC2164 datasheet(13/39 Pages) MICREL

13 / 39 page

Micrel, Inc.

MIC2164/-2/-3/C

September 2010

M9999-091310-D

Functional Description

The MIC2164/-2/-3 is an adaptive on-time synchronous

buck controller family built for low cost and high

performance. They are designed for a wide input voltage

range from 3V to 28V and for high output power buck

converters. An estimated-ON-time method is applied in

MIC2164/-2/-3 to obtain a constant switching frequency

and to simplify the control compensation. The over-

current protection is implemented without the use of an

external sense resistor. It includes an internal soft-start

function which reduces the power supply input surge

current at start-up by controlling the output voltage rise

time.

Theory of Operation

The MIC2164/-2/-3 is a adaptive on-time buck controller

family. Figure 1 illustrates the block diagram for the

control loop. The output voltage variation will be sensed

by the MIC2164/-2/-3 feedback pin FB via the voltage

divider R1 and R2, and compared to a 0.8V reference

voltage VREF at the error comparator through a low gain

transconductance (gm) amplifier, the amplifier improves

the MIC2164/-2/-3 converter output voltage regulation. If

the FB voltage decreases and the output of the gm

amplifier is below 0.8V, The error comparator will trigger

the control logic and generate an ON-time period, in

which DH pin is logic high and DL pin is logic low. The

ON-time period length is predetermined by the “FIXED

TON ESTIMATION” circuitry:

HSD

OUT

ed)

ON(estimat

(1)

where VOUT is the output voltage, VHSD is the power

stage input voltage, and fSW is the switching frequency

(300kHz for MIC2164, 600kHz for MIC2164-2, and

1MHz for MIC2164-3).

After ON-time period, the MIC2164/-2/-3 goes into the

OFF-time period, in which DH pin is logic low and DL pin

is logic high. The OFF-time period length is depending

on the FB voltage in most cases. When the FB voltage

decreases and the output of the gm amplifier is below

0.8V, then the ON-time period is trigger and the OFF-

time period ends. If the OFF-time period decided by the

FB voltage is less than the minimum OFF time TOFF(min),

which is about 363ns typical, then the MIC2164/-2/-3

control logic will apply the TOFF(min) instead. TOFF(min) is

required by the BST charging.

The maximum duty cycle is obtained from the 363ns

TOFF(min):

OFF(min)

363ns

Dmax

−

where Ts = 1/fSW.

It is not recommended to use MIC2164/-2/-3 with a OFF

time close to TOFF(min) at the steady state. Also, as VOUT

increases, the internal ripple injection will increase and

reduce the line regulation performance. Therefore, the

maximum output voltage of the MIC2164/-2/-3 should be

limited to 5.5V. If a higher output voltage is required, use

the MIC2176 instead. Please refer to “Setting Output

Voltage” subsection in “Application Information” for more

details.

The estimated-ON-time method results in a constant

switching frequency in MIC2164/-2/-3. The actual ON

time is varied with the different rising and falling time of

the external MOSFETs. Therefore, the type of the

external MOSFETs, the output load current, and the

control circuitry power supply VIN will modify the actual

ON time and the switching frequency. Also, the minimum

TON results in a lower switching frequency in the high

VHSD and low VOUT applications, such as 24V to 1.0V

MIC2164-3 application. The minimum TON measured on

the MIC2164 evaluation board is about 138ns. During

the load transient, the switching frequency is changed

due to the varying OFF time.

To illustrate the control loop, the steady-state scenario

and the load transient scenario are analyzed. For easy

analysis, the gain of the gm amplifier is assumed to be 1.

With this assumption, the inverting input of the error

comparator is the same as the FB voltage. Figure 2

shows the MIC2164/-2/-3 control loop timing during the

steady-state. During the steady-state, the gm amplifier

senses the FB voltage ripple, which is proportional to the

output voltage ripple and the inductor current ripple, to

trigger

the

ON-time

period.

The

time

predetermined by the estimation. The ending of OFF

time is controlled by the FB voltage. At the valley of the

FB voltage ripple, which is below than VREF, OFF period

ends and the next ON-time period is triggered through

the control logic circuitry.

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