M41T82RM6F datasheet(12/61 Pages) STMICROELECTRONICS

12 / 61 page

Operation

M41T82-M41T83

12/61

Doc ID 12578 Rev 12

Operation

The M41T8x clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 32 bytes

contained in the device can then be accessed sequentially in the following order:

●

1st byte: tenths/hundredths of a second register

●

2nd byte: seconds register

●

3rd byte: minutes register

●

4th byte: century/hours register

●

5th byte: day register

●

6th byte: date register

●

7th byte: month register

●

8th byte: year register

●

9th byte: digital calibration register

●

10th byte: watchdog register

●

11th - 15th bytes: alarm 1 registers

●

16th byte: flags register

●

17th byte: timer value register

●

18th byte: timer control register

●

19th byte: analog calibration register

●

20th byte: square wave register

●

21st - 25th bytes: alarm 2 registers

●

26th - 32nd bytes: user RAM

The M41T8x clock continually monitors VCC for an out-of-tolerance condition. Should VCC

fall below VRST, the device terminates an access in progress and resets the device address

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from an out-of-tolerance system. The power input will also

be switched from the VCC pin to the battery when VCC falls below the battery back-up

switchover voltage (VSO = VRST). At this time the clock registers will be maintained by the

attached battery supply. As system power returns and VCC rises above VSO, the battery is

disconnected, and the power supply is switched to external VCC.

M41T82RM6F датащи(PDF) 12 Page - STMicroelectronics

M41T82RM6F датащи(HTML) 12 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

датащи скачать

ссылки URL