80333 datasheet(21/75 Pages) INTEL

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80333

Datasheet

Intel® 80333 I/O Processor Datasheet

May 2005

Order Number: 305433, Revision: 002

B_IRDY#

I/O

Sync(B)

Rst(B)

B PCI Bus Initiator Ready indicates the initiating agent’s ability to

complete the current data phase of the transaction. During a write,

it indicates that valid data is present on the Address/Data bus.

During a read, it indicates the processor is ready to accept the

data.

B_TRDY#

I/O

Sync(B)

Rst(B)

B PCI Bus Target Ready indicates the target agent’s ability to

complete the current data phase of the transaction. During a read,

it indicates that valid data is present on the Address/Data bus.

During a write, it indicates the target is ready to accept the data.

B_STOP#

I/O

Sync(B)

Rst(B)

B PCI Bus Stop indicates a request to stop the current transaction

on the PCI bus.

B_DEVSEL#

I/O

Sync(B)

Rst(B)

B PCI Bus Device Select is driven by a target agent that has

successfully decoded the address. As an input, it indicates

whether or not an agent has been selected.

B_LOCK#

I/O

Sync(B)

Rst(B)

B PCI Bus Lock indicates whether or not a transaction is

establishing a LOCK across the bridge.

B_SERR#

I/O

Sync(B)

Rst(B)

B PCI Bus System Error is driven for address parity errors on the

PCI bus.

B_PERR#

I/O

Sync(B)

Rst(B)

B PCI Bus Parity Error is asserted when a data parity error

occurs during a PCI bus transaction.

B_M66EN

1I/O

B PCI Bus 66 MHz Enable indicates the speed of the PCI bus.

When this signal is sampled high the PCI bus speed is 66 MHz,

when low, the bus speed is 33 MHz.

B_PME#

Sync(B)

Power Management Event signal is used to request a change in

the device or system power state.

B_PCIXCAP

B PCI-X Capability Analog pad that selects PCI/X mode and

frequency capabilities. Non-standard, special purpose analog pin.

B_CLKO[4:0]

B PCI Bus Output Clocks are used to drive external logic on the

secondary PCI bus.

B_CLKOUT

B PCI Bus Output Clock is used to drive B_CLKIN when

secondary bus clocks are enabled.

B_CLKIN

B PCI Bus Input Clock provides the timing for all PCI

transactions. Typically connected on the board to B_CLKOUT.

Provides timing clock for all B-segment PCI interfaces.

B_RST#

B PCI BUS RESET is an output based on RSTIN# or PWRGD. It

brings PCI-specific registers, sequencers, and signals to a

consistent state. When RSTIN# is asserted or PWRGD is

deasserted, or the secondary bridge reset bit is asserted, it causes

B_RST# to assert and:

•

PCI output signals are driven to a known consistent state.

•

PCI bus interface output signals are three-stated.

•

open drain signals such as B_SERR# are floated

B_RST# may be asynchronous to B_CLKIN when asserted or

deasserted. Although asynchronous, deassertion must be

guaranteed to be a clean, bounce-free edge.

B_RCOMP

1I/O

PCI Resistor Compensation Pin is an analog pad that connects

to a board resistor to control all B segment PCI output driver

strengths (analog).

Total

106

Table 7.

B PCI (Slot Expansion) Bus Signals (Sheet 2 of 2)

Name

Count

Type

Description

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