430 datasheet(58/71 Pages) INTEL

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Package Mechanical Specifications and Pin Information

Datasheet

DSTBP[3:0]#

Input/

Output

Data strobe used to latch in D[63:0]#.

FERR#/PBE#

Output

FERR# (Floating-point Error)PBE#(Pending Break Event) is a

multiplexed signal and its meaning is qualified with STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating point

when the processor detects an unmasked floating-point error.

FERR# is similar to the ERROR# signal on the Intel 387 coprocessor,

and is included for compatibility with systems using MS-DOS*-type

floating-point error reporting. When STPCLK# is asserted, an

assertion of FERR#/PBE# indicates that the processor has a pending

break event waiting for service. The assertion of FERR#/PBE#

indicates that the processor should be returned to the Normal state.

When FERR#/PBE# is asserted, indicating a break event, it will

remain asserted until STPCLK# is deasserted. Assertion of PREQ#

when STPCLK# is active will also cause an FERR# break event.

For additional information on the pending break event functionality,

including identification of support of the feature and enable/disable

information, refer to Volume 3 of the IA 32 Intel® Architecture

Software Developer’s Manual and the Intel® Processor Identification

and CPUID Instruction application note.

For termination requirements, please contact your Intel

representative.

GTLREF

Input

GTLREF determines the signal reference level for AGTL+ input pins.

GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+

receivers to determine if a signal is a logical 0 or logical 1.

HIT#/

HITM#

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Either FSB agent may assert both HIT# and

HITM# together to indicate that it requires a snoop stall, which can

be continued by reasserting HIT# and HITM# together.

IERR#

Output

IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the FSB. This transaction may optionally

be converted to an external error signal (e.g., NMI) by system core

logic. The processor will keep IERR# asserted until the assertion of

RESET#, BINIT#, or INIT#.

For termination requirements, please contact your Intel

representative.

Table 15.

Signal Description (Sheet 4 of 8)

Name

Type

Description

Signals

Associated Strobe

D[15:0]#, DINV[0]#

DSTBP[0]#

D[31:16]#, DINV[1]#

DSTBP[1]#

D[47:32]#, DINV[2]#

DSTBP[2]#

D[63:48]#, DINV[3]#

DSTBP[3]#

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