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Datasheet

Electrical Specifications

2.3.1

VCC Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low power states, must be

provided by the voltage regulator solution (VR). For more details on this topic, refer to the Voltage

Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

2.3.2

FSB GTL+ Decoupling

The Pentium 4 processor in the 775-land package integrates signal termination on the die as well as

incorporating high frequency decoupling capacitance on the processor package. Decoupling must

also be provided by the system baseboard for proper GTL+ bus operation.

2.3.3

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.

As in previous generation processors, the Pentium 4 processor in the 775-land package core

frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set

at its default ratio during manufacturing. No user intervention is necessary, and the processor will

automatically run at the speed indicated on the package.

The Pentium 4 processor in the 775-land package uses a differential clocking implementation. For

more information on the Pentium 4 processor in the 775-land package clocking, refer to the

CK410/CK410M Clock Synthesizer/Driver Specification.

Table 2-1. Core Frequency to FSB Multiplier Configuration

Multiplication of System Core

Frequency to FSB Frequency

Core Frequency (200 MHz

BCLK/800 MHz FSB)

Notes1, 2

NOTES:

Individual processors operate only at or below the rated frequency.

Listed frequencies are not necessarily committed production frequencies.

1/14

2.80 GHz

1/15

3 GHz

1/16

3.20 GHz

1/17

3.40 GHz

1/18

3.60 GHz

1/19

3.80 GHz

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