82G33 datasheet(7/437 Pages) INTEL

7 / 437 page

Datasheet

6.1.18

PMLIMIT1—Prefetchable Memory Limit Address.......................... 195

6.1.19

PMBASEU1—Prefetchable Memory Base Address ........................ 196

6.1.20

PMLIMITU1—Prefetchable Memory Limit Address........................ 197

6.1.21

CAPPTR1—Capabilities Pointer................................................. 198

6.1.22

INTRLINE1—Interrupt Line...................................................... 198

6.1.23

INTRPIN1—Interrupt Pin......................................................... 198

6.1.24

BCTRL1—Bridge Control ......................................................... 199

6.1.25

PM_CAPID1—Power Management Capabilities............................ 201

6.1.26

PM_CS1—Power Management Control/Status ............................ 202

6.1.27

SS_CAPID—Subsystem ID and Vendor ID Capabilities ................ 203

6.1.28

SS—Subsystem ID and Subsystem Vendor ID ........................... 203

6.1.29

MSI_CAPID—Message Signaled Interrupts Capability ID.............. 204

6.1.30

MC—Message Control............................................................. 204

6.1.31

MA—Message Address............................................................ 205

6.1.32

MD—Message Data ................................................................ 205

6.1.33

PEG_CAPL—PCI Express*-G Capability List................................ 206

6.1.34

PEG_CAP—PCI Express*-G Capabilities..................................... 206

6.1.35

DCAP—Device Capabilities ...................................................... 207

6.1.36

DCTL—Device Control ............................................................ 208

6.1.37

DSTS—Device Status ............................................................. 209

6.1.38

LCAP—Link Capabilities .......................................................... 210

6.1.39

LCTL—Link Control ................................................................ 212

6.1.40

LSTS—Link Status ................................................................. 214

6.1.41

SLOTCAP—Slot Capabilities..................................................... 215

6.1.42

SLOTCTL—Slot Control ........................................................... 216

6.1.43

SLOTSTS—Slot Status............................................................ 219

6.1.44

RCTL—Root Control ............................................................... 220

6.1.45

RSTS—Root Status ................................................................ 221

6.1.46

PEGLC—PCI Express*-G Legacy Control.................................... 222

6.1.47

VCECH—Virtual Channel Enhanced Capability Header ................. 223

6.1.48

PVCCAP1—Port VC Capability Register 1 ................................... 223

6.1.49

PVCCAP2—Port VC Capability Register 2 ................................... 224

6.1.50

PVCCTL—Port VC Control........................................................ 224

6.1.51

VC0RCAP—VC0 Resource Capability ......................................... 225

6.1.52

VC0RCTL—VC0 Resource Control ............................................. 226

6.1.53

VC0RSTS—VC0 Resource Status .............................................. 227

6.1.54

RCLDECH—Root Complex Link Declaration Enhanced.................. 228

6.1.55

ESD—Element Self Description ................................................ 228

6.1.56

LE1D—Link Entry 1 Description ............................................... 229

6.1.57

LE1A—Link Entry 1 Address .................................................... 229

6.1.58

PEGSSTS—PCI Express*-G Sequence Status ............................. 230

Direct Memory Interface (DMI) Registers.......................................................... 232

7.1

Direct Memory Interface (DMI) Configuration Register Details................... 233

7.1.1

DMIVCECH—DMI Virtual Channel Enhanced Capability ................ 233

7.1.2

DMIPVCCAP1—DMI Port VC Capability Register 1 ....................... 234

7.1.3

DMIPVCCAP2—DMI Port VC Capability Register 2 ....................... 234

7.1.4

DMIPVCCTL—DMI Port VC Control............................................ 235

7.1.5

DMIVC0RCAP—DMI VC0 Resource Capability ............................. 235

7.1.6

DMIVC0RCTL0—DMI VC0 Resource Control ............................... 236

7.1.7

DMIVC0RSTS—DMI VC0 Resource Status.................................. 237

7.1.8

DMIVC1RCAP—DMI VC1 Resource Capability ............................. 237

7.1.9

DMIVC1RCTL1—DMI VC1 Resource Control ............................... 238

7.1.10

DMIVC1RSTS—DMI VC1 Resource Status.................................. 239

7.1.11

DMILCAP—DMI Link Capabilities .............................................. 239

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