Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

M48T59, M48T59Y, M48T59V

Clock operations

19/32

3.10

Century bit

Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the

CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or

from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'

CB will not toggle.

Note:

The WRITE Bit must be set in order to write to the CENTURY Bit.

3.11

Initial power-on defaults

Upon application of power to the device, the following register bits are set to a '0' state:

WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT (see Table 7).

Table 7.

Default values

3.12

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in

Figure 12 on page 20) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, it is recommended to connect a

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface

mount.

Condition

W

R

FT

AFE

ABE

Watchdog

1.

WDS, BMB0-BMB4, RBO, RB1.

Initial power-up

2.

State of other control bits undefined.

00

000

0

3.

State of other control bits remains unchanged.

00

000

0

4.

Assuming these bits set to '1' prior to power-down.

00

011

0