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M95010 датащи(PDF) 16 Page - STMicroelectronics

номер детали M95010
подробное описание детали  4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock
PDF  43 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95010 датащи(HTML) 16 Page - STMicroelectronics

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Instructions
M95040, M95020, M95010
16/43
Doc ID 6512 Rev 8
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 4.
If an invalid instruction is sent (one not contained in Table 4), the device automatically
deselects itself.
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 7.
Write Enable (WREN) sequence
Table 4.
Instruction set
Instruction
Description
Instruction Format
WREN
Write Enable
0000 X110(1)
1.
X = Don’t Care.
WRDI
Write Disable
0000 X100(1)
RDSR
Read Status Register
0000 X101(1)
WRSR
Write Status Register
0000 X001(1)
READ
Read from Memory Array
0000 A8011
(2)
2.
A8 = 1 for the upper half of the memory array of the M95040, and 0 for the lower half, and is Don’t Care for
other devices.
WRITE
Write to Memory Array
0000 A8010
(2)
C
D
AI01441D
S
Q
2
1
34567
High Impedance
0
Instruction



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