M48T129V, M48T129Y

Clock operations

Doc ID 5710 Rev 4

17/28

Figure 11.

Backup mode alarm waveforms

3.7

Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the watchdog

register, address 1FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower

order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1

second, and 11 = 4 seconds. The amount of time-out is then determined to be the

multiplication of the five-bit multiplier value with the resolution. (For example: writing

00001110 in the watchdog register = 3*1 or 3 seconds).

Note:

Accuracy of timer is a function of the selected resolution.

If the processor does not reset the timer within the specified period, the M48T129Y/V sets

the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.

WDF is reset by reading the flags register (address 1FFF0h). The most significant bit of the

watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will

activate the IRQ/FT pin when timed-out. When WDS is set to a '1,' the watchdog will output

a negative pulse on the RST pin for 40 to 200 ms. The watchdog register and the FT bit will

reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.'

The watchdog timer can be reset by two methods:

1.

a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI);

or

2.

the microprocessor can perform a WRITE of the watchdog register.

watchdog will be reset on each transition (edge) seen by the WDI pin. In the order to

perform a software reset of the watchdog timer, the original time-out period can be written

into the watchdog register, effectively restarting the count-down cycle.

AI01678C

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

tREC