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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC24FJ64GA датащи(PDF) 89 Page - Microchip Technology |
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PIC24FJ64GA датащи(HTML) 89 Page - Microchip Technology |
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89 / 262 page  © 2008 Microchip Technology Inc. Preliminary DS39881C-page 87 PIC24FJ64GA004 FAMILY 7.0 OSCILLATOR CONFIGURATION The oscillator system for PIC24FJ64GA004 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes • On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown A simplified diagram of the oscillator system is shown in Figure 7-1. FIGURE 7-1: PIC24FJ64GA004 FAMILY CLOCK DIAGRAM Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 6. Oscillator” (DS39700). PIC24FJ64GA004 Family Secondary Oscillator SOSCEN Enable Oscillator SOSCO SOSCI Clock Source Option for Other Modules OSCI OSCO Primary Oscillator XT, HS, EC CPU Peripherals CLKDIV<10:8> WDT, PWRT 8 MHz FRCDIV 31 kHz (nominal) FRC Oscillator LPRC Oscillator SOSC LPRC Clock Control Logic Fail-Safe Clock Monitor CLKDIV<14:12> FRC CLKO (nominal) 4 x PLL XTPLL, HSPLL ECPLL,FRCPLL 8 MHz 4 MHz |
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