MRF49XA datasheet(21/102 Pages) MICROCHIP

21 / 102 page

Preliminary

DS70590B-page 19

MRF49XA

bit 10

LBTD:

Low Battery Threshold Detect bit

Indicates whether the battery or supply voltage is below the preprogrammed threshold limit.

= Supply voltage is below threshold

= Normal supply voltage feed

bit 9

FIFOEM:

FIFO Empty bit

Indicates whether the receive FIFO is empty or filled.

= FIFO is empty

= FIFO is filled

bit 8

ATRSSI:

Antenna Tuning and Received Signal Strength Indicator bit

Transmit mode:

The bit indicates that the antenna tuning circuit has detected a strong RF signal.

= Strong RF signal present

= Weak or absence of RF signal

Receive mode:

The bit indicates that the incoming RF signal is above the preprogrammed digital RSSI limit.

= RF signal is above the threshold value set

= RF signal is less than the threshold value set

bit 7

DQDO:

Data Quality Detect/Indicate Output bit

Indicates good data quality output.

= Quality data is detected

= Quality data is unavailable

bit 6

CLKRL:

Clock Recovery Lock bit

Indicates clock recovery is locked.

= Clock recovery locked

= Clock recovery unlocked

bit 5

AFCCT:

Automatic Frequency Control Cycle Toggle bit

For each AFC cycle run, this bit toggles between logic ‘1’ and logic ‘0’.

= AFC cycle has occurred

= No AFC in this cycle

bit 4

OFFSV:

Offset Sign Value bit

Indicates the measured difference or frequency offset of any AFC cycle (sign of the offset value).

= Higher than the chip frequency

= Lower than the chip frequency

bit 3-0

OFFSB<3:0>:

Offset bits

The offset value to be added to the frequency control parameter (internal PLL).(4)

= Result is negative

= Result is positive

Note:

See Appendix A: “Read Sequence and Packet Structures” for the STSREG read sequence,.

STSREG: STATUS READ REGISTER (POR: 0x0000)(1) (CONTINUED)

Note 1:

All register commands begin with logic ‘1’ and only the STATUS register read command begins with logic ‘0’.

This bit is multiplexed for Transmit or Receive mode.

See the FFBC bits (FIFORSTREG<3:0>) in Register 2-10.

To get accurate values, the AFC should be disabled during the read by clearing the FOFEN bit

(AFCCREG<0>). The AFC offset value (OFFSB bits in the status word) is represented as a two’s

complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by

the current PLL frequency step from CFSREG (FREQB<11:0>).

This bit is cleared after STSREG is read.

MRF49XA датащи(PDF) 21 Page - Microchip Technology

MRF49XA датащи(HTML) 21 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL