MCP9843 datasheet(38/62 Pages) MICROCHIP

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MCP9843/98243

DS22153C-page 38

5.3.3.1

Software Write Protect (SWP)

The SWP feature is invoked by writing to the write-

protect register. This is done by sending an Address

Byte similar to a normal Write command. Figure 5-17

shows the timing diagram. SWP can be cleared using

the CWP command. See Section 5.3.3.2 “Clear Write

Protect (CWP)”

The Slave Address bits need to correspond to the

address pin logic configuration. For SWP, a high

voltage VHV needs to be applied to the A0 pin and the

corresponding slave address needs to be set to ‘1’, as

shown in Table 5-3. Both A2 and A1 pins are grounded

and the corresponding slave address bits are set to ‘0’.

The device response in this mode is shown in Table 5-

4 and Table 5-5.

FIGURE 5-15:

Timing Diagram for Setting Software Write Protect (See Section 4.0 “Serial

Communication”).

5.3.3.2

Clear Write Protect (CWP)

The CWP feature is invoked by writing to the clear

write-protect register. This is done by sending an

Address Byte similar to a normal Write command.

Figure 5-17 shows the timing diagram. CWP clears

SWP only. PWP can not be cleared using this

command.

The Slave Address bits need to correspond to the

address pin logic configuration. For CWP, a high

voltage VHV needs to be applied to the A0 pin and the

corresponding slave address needs to be set to ‘1’.

The A1 pin is set to VDD and the corresponding slave

address bit is set to ‘1’. And A2 pins is set to ground

and the corresponding slave address bits are set to ‘0’.

Table 5-3 shows the bit configuration. The device

response in this mode is shown in Table 5-4 and

Table 5-5.

FIGURE 5-16:

Timing Diagram for Setting Clear Write Protect (See Section 4.0 “Serial

Communication”).

SDA

345

SCL

Address Byte

MCP98243

567

Data

Word Address

MCP98243

Note:

Apply VHV at A0 pin and connect GND to A1 and A2 pins to initiate SWP cycle.

SDA

345

SCL

Address Byte

MCP98243

567

Data

Word Address

MCP98243

Note:

Apply VHV at A0 pin, apply VDD at A1 pin, connect A2 pin to GND to initiate CWP cycle.

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