ADS1174IPAPR datasheet(13/39 Pages) TI1

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VOLTAGE REFERENCE INPUTS

CLOCK INPUT (CLK)

ESD

Protection

AVDD

VREFN

VREFP

AGND

VREFP

VREFN

eff

´ (6.75MHz/f

)

MOD

5.2kW

N =numberofactivechannels.

ADS1174

ADS1178

www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008

If these conditions are possible, external Schottky

(VREFP, VREFN)

clamp diodes or series resistors may be required to

limit the input current to safe levels (see Absolute

The voltage reference for the ADS1174/78 ADC is

Maximum Ratings table).

the differential voltage between VREFP and VREFN:

VREF = (VREFP – VREFN). The voltage reference is

Note that the valid operating range of the reference

common to all channels. The reference inputs use a

inputs is limited to the following:

structure similar to that of the analog inputs with the

–0.1V

≤ VREFN ≤ 0.1V

equivalent circuitry on the reference inputs shown in

Figure 10. As with the analog inputs, the load

VREFN + 0.5V

≤ VREFP ≤ VREFN + 3.1V

presented by the switched capacitor can be modeled

A high-quality reference voltage with the appropriate

with an effective impedance, as shown in Figure 11.

drive strength is essential for achieving the best

However, the reference input impedance depends on

performance from the ADS1174/78. Noise and drift

the number of active (enabled) channels in addition to

the

reference

degrade

overall

system

fMOD. As a result of the change of reference input

performance. See the Application Information section

impedance

caused

enabling

and

disabling

for example reference circuits.

channels, the regulation and settling time of the

external reference should be noted, so as not to

affect the readings of other channels.

The ADS1174/78 requires a clock input for operation.

Each ADS1174/78 converter operates from the same

clock input. At the maximum data rate, the clock input

can be either 27MHz or 13.5MHz (5.4MHz, low-power

mode), determined by the setting of the CLKDIV

input. The selection of the external clock frequency

(fCLK) does not affect the resolution (the oversampling

ratio, OSR, remains fixed) or power dissipation of the

ADS1174/78. However, a slower fCLK can reduce the

power consumption of an external clock driver. The

output data rate scales with clock frequency, down to

a minimum clock frequency of fCLK = 100kHz. Table 4

summarizes the ratio of clock input frequency (fCLK) to

data

rate

(fDATA),

maximum

data

rate

and

corresponding maximum clock input for the two

Figure 10. Equivalent Reference Input Circuitry

operating modes.

Table 4. Clock Input Options

MODE

fCLK

DATA RATE

SELECTION

(MHz)

CLKDIV

fCLK/fDATA

(SPS)

512

High-Speed

52,734

13.5

256

2,560

Low-Power

10,547

5.4

512

As with any high-speed data converter, a high-quality,

Figure 11. Effective Reference Impedance

low-jitter clock is essential for optimum performance.

Crystal clock oscillators are the recommended clock

source. Make sure to avoid excess ringing on the

ESD diodes protect the reference inputs. To keep

clock input; keeping the clock trace as short as

these diodes from turning on, make sure the voltages

possible using a 50

Ω series resistor, placed close to

on the reference pins do not go below AGND by

the source end, often helps.

more than 0.4V, and likewise do not exceed AVDD by

0.4V.

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