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74AHCT240D датащи(PDF) 9 Page - NXP Semiconductors |
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74AHCT240D датащи(HTML) 9 Page - NXP Semiconductors |
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9 / 16 page ![]() 74AHC_AHCT240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 26 November 2010 9 of 16 NXP Semiconductors 74AHC240; 74AHCT240 Octal buffer/line driver; inverting; 3-state Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7. Load circuitry for switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC240 VCC 3.0 ns 15 pF, 50 pF 1 k open GND VCC 74AHCT240 3.0 V 3.0 ns 15 pF, 50 pF 1 k open GND VCC |
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