DS21552 datasheet(7/137 Pages) MAXIM

7 / 137 page

DS21352/DS21552

7 of 137

3. INTRODUCTION

The DS21352/552 are 3.3V/5V superset versions of the popular DS2152 T1 single-chip transceiver

offering the new features listed below. All of the original features of the DS2152 have been retained and

software created for the original devices is transferable into the DS21352/552.

NEW FEATURES (after the DS2152)

Interleaving PCM Bus Operation

Integral HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation

IEEE 1149.1 JTAG-Boundary Scan Architecture

3.3V (DS21352 only) supply

FEATURES

option for non–multiplexed bus operation

crystal–less jitter attenuation

3.3V I/O on all SCTs

additional hardware signaling capability including:

– receive signaling reinsertion to a backplane multiframe sync

– availability of signaling in a separate PCM data stream

– signaling freezing

– interrupt generated on change of signaling data

ability to calculate and check CRC6 according to the Japanese standard

ability to pass the F–Bit position through the elastic stores in the 2.048 MHz backplane mode

programmable in–band loop code generator and detector

per channel loopback and idle code insertion

RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

8.192 MHz clock output synthesized to RCLK

HDLC controller can be configured for FDL

addition of hardware pins to indicate carrier loss & signaling freeze

line interface function can be completely decoupled from the framer/formatter to allow:

– interface to optical, HDSL, and other NRZ interfaces

– be able to “tap” the transmit and receive bipolar data streams for monitoring purposes

– be able corrupt data and insert framing errors, CRC errors, etc.

transmit and receive elastic stores now have independent backplane clocks

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