ISL97635 datasheet(13/28 Pages) INTERSIL

13 / 28 page

FN6434.2

December 22, 2008

PWMO pin for DPST mode operation which will be described

in “PWM Dimming Frequency Adjustment” on page 13.

For example, if the SMBus controlled PWM duty is 80%

dimming at 200Hz (see CFPWM Equation 12) and the

external PWMI duty cycle is 60% dimming at 1kHz, the

resultant PWM duty cycle is 48% dimming at 200Hz.

Method 4 (Analog Mode, DC-to-PWM Mode)

By overdriving the PWMO pin with a DC voltage between

0.21V and 1.21V, the average LED current of each channel

is controlled by the internally generated PWM signal, as

shown in Equation 11:

Where BRT is the value held in Register 0x00 (default

setting 0xFF). The PWMO pin is internally driven to 0.21V

via a 40k

Ω resistor when the EN/PWMI pin is in logic high,

any overdrive circuit will need to be able to drive up to 40µA

in order to overcome this.

The DC-to-PWM controlled PWM frequency is adjusted by a

capacitor at the FPWM pin, which will be described in “PWM

Dimming Frequency Adjustment” on page 13.

For example, if PWMO is applied with a DC voltage

≥ 1.21V,

the output will be zero. On the other hand, if the PWMO is

applied with a DC voltage

≤ 0.21V, the PWM duty cycle will

be at its maximum. If the PWMO pin is applied with a DC

voltage of 0.31V, the PWM duty cycle will be at 90% at

200Hz if CFPWM = 27nF.

PWM Dimming Frequency Adjustment

(Applicable to SMBus controlled PWM, DPST, and

DC-to-PWM Modes)

Except for the external PWM dimming mode where the

frequency follows the external signals, the dimming

frequencies of the other modes are set by an external

capacitor CFPWM at the FPWM pin, as shown in Equation 12:

where FPWM is the desirable PWM dimming frequency.

For example, if FPWM = 200Hz, CFPWM = 5.4µF/200 = 27nF

The PWM dimming frequency can be for example 20kHz but

there are a minimum on and off time requirements such that

the dimming will be in the range of 10% to 99.5%. If the

dimming frequency is below 5kHz, the dimming range can

be 1% to 99.5%.

In the DPST and DC-to-PWM modes, a CPWMO capacitor is

also needed. An internal 40k

Ω and an external C

PWMO at the

PWMO pin form a low pass network to filter the PWMI to an

averaged DC. As a result, the time constant of the 40k

Ω and

CPWMO should be significantly larger than the external PWMI

period, t, such that Equation 13 will show:

For example, if FPWM is 200Hz and an external PWMI is

1kHz and above, a 220nF CPWMO can be chosen that allows

the external PWMI signal to be filtered as an averaged DC.

Also, the FPWM frequency in the DPST mode should be

limited between 100Hz to 2kHz and at least five times

smaller than the external PWMI frequency when DPST

mode is used.

Switching Frequency

An internal clock of 1.2MHz is used for the boost regulator

control of the LX pin in default. There are 2 levels of

switching frequencies: 600kHz or 1.2MHz. Each can be

programmed in the Configuration Register 0x08 bit 2. The

default switching frequency is at 1.2MHz.

5V Low Dropout Regulator

A 5.2V LDO regulator is present at the VDC pin to develop the

necessary low voltage supply, which is used by the chips

internal control circuitry. Because VDC is an LDO pin, it

requires a bypass capacitor of 1µF or more for the regulation.

For applications with an input voltage

≤ 5.5V, VIN and VDC

pins can be connected together. Low input voltage also allows

only lower output voltage applications only with the maximum

boost ratio defined in “Components Selections” on page 24.

The VDC pin can be used as a coarse reference with a few

mA sourcing capability.

In-rush Control and Soft-start

The ISL97635 has separately built-in independent inrush

control and soft-start functions. The inrush control function is

built around the short circuit protection FET, and is only

available in applications, which include this device. At

start-up, the fault protection FET is turned on slowly due to a

30µA pull-down current output from the FAULT pin. This

discharges the fault FET's gate-source capacitance, turning

on the FET in a controlled fashion. As this happens, the

output capacitor is charged slowly through the weakly turned

on FET before it becomes fully enhanced. This results in a

low in-rush current. This current can be further reduced by

adding a capacitor (in the 1nF to 5nF range) across the

gate-source terminals of the FET.

Once the chip detects that the fault protection FET is turned

on hard, it is assumed that in-rush has completed. At this

point, the boost regulator will begin to switch and the current

in the inductor will ramp-up. The current in the boost power

switch is monitored and the switching is terminated in any

cycle where the current exceeds the current limit. The

ISL97635 includes a soft-start feature where this current limit

starts at a low value (375mA). This is stepped up to the final

3A current limit in 7 further steps of 375mA. These steps will

happen over a 1ms total time, such that after 1ms, the final

limit will be reached. This allows the output capacitor to be

LED ave

()

LED

BRT 255

V PWMO

() 0.21

–

()

–

()

⁄

(EQ. 11)

FPWM

5.4

μFFPWM

⁄

(EQ. 12)

40k

Ω x C

PWMO >t

(EQ. 13)

ISL97635

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