LTM4618 datasheet(14/24 Pages) LINER

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LTM4618

4618f

APPLICATIONS INFORMATION

is really the sum of the

θJCbottom and the thermal re-

sistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured at speciﬁed distance from

the package, using a two sided, two layer board.

This board is described in JESD 51-9.

A graphical representation of the forementioned thermal

resistances is given in Figure 6; blue resistances are con-

tained within the μModule, whereas green resistances are

external to the μModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters deﬁned by JESD 51-12 or provided in the

Pin Conﬁguration section replicates or conveys normal

operating conditions of a μModule. For example, in actual

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sively through the top or exclusively through bottom of the

μModule—as the standard deﬁnes for

θJCtopandθJCbottom,

respectively. In practice, power loss is thermally dissipated

in both directions away from the package—granted, in the

absence of a heat sink and airﬂow, a majority of the heat

ﬂow is into the board.

Within a SIP (System-In-Package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacriﬁcing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably deﬁne and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the μModule and the speciﬁed PCB with all

of the correct material coefﬁcients along with accurate

power loss source deﬁnitions; (2) this model simulates

a software-deﬁned JEDEC environment consistent with

JSED51-9 to predict power loss heat ﬂow and temperature

readings at different interfaces that enable the calculation

of the JEDEC-deﬁned thermal resistance values; (3) the

model and FEA software is used to evaluate the μModule

with heat sinks and airﬂow; (4) having solved for and

analyzed these thermal resistance values and simulated

various operating conditions in the software model, a

thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled-envi-

ronment chamber while operating the device at the same

power loss as that which was simulated. An outcome of

this process and due-diligence yields a set of derating

curves provided in other sections of this data sheet. After

these laboratory tests have been performed and correlated

to the μModule model, then the

θJB and θBA are summed

together to correlate quite well with the μModule model

with no air ﬂow or heat sinking in a properly deﬁne cham-

ber. This

θJB+ θBA value is shown in the Pin Conﬁguration

section and should accurately equal the

θJA value because

approximately 100% of power loss ﬂows from the junc-

tion through the board into ambient with no airﬂow or top

mounted heat sink.

4618 F06

μMODULE DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

CASE (BOTTOM)-TO-BOARD

RESISTANCE

Figure 6. Graphical Representation of JESD51-12 Thermal Coefﬁcients

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