PIC16F720-ESLASHML datasheet(158/244 Pages) MICROCHIP

158 / 244 page

PIC16F/LF720/721

DS41430A-page 158

 2010 Microchip Technology Inc.

SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit

= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t

care” in Transmit mode. SSPOV must be cleared in software in either mode.

= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

= Enables the serial port and configures the SDA and SCL pins as serial port pins(2)

= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

= Release control of SCL

= Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0

SSPM<3:0>: Synchronous Serial Port mode Select bits

0110

= I2C Slave mode, 7-bit address

0111

= I2C Slave mode, 10-bit address

1000

= Reserved

1001

= Load SSPMSK register at SSPADD SFR Address(1)

1010

= Reserved

1011

= I2C Firmware Controlled Master mode (Slave Idle)

1100

= Reserved

1101

= Reserved

1110

= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111

= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register.

2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.

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