PIC16F720-ESLASHML datasheet(149/244 Pages) MICROCHIP

149 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 149

PIC16F/LF720/721

17.2

I2C Mode

The SSP module, in I2C mode, implements all slave

functions except general call support. It provides

interrupts on Start and Stop bits in hardware to facilitate

firmware implementations of the master functions. The

SSP module implements the I2C Standard mode

specifications:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

• Start and Stop bit interrupts enabled to support

firmware Master mode

•Address masking

Two pins are used for data transfer; the SCL pin (clock

line) and the SDA pin (data line). The user must

configure the two pin’s data direction bits as inputs in

the appropriate TRIS register. Upon enabling I2C

mode, the I2C slew rate limiters in the I/O pads are

controlled by the SMP bit of SSPSTAT register. The

SSP module functions are enabled by setting the

SSPEN bit of SSPCON register.

Data is sampled on the rising edge and shifted out on

the falling edge of the clock. This ensures that the SDA

signal is valid during the SCL high time. The SCL clock

input must have minimum high and low times for proper

operation.

Refer

Section 23.0

“Electrical

Specifications”.

FIGURE 17-7:

I2C™ MODE BLOCK

DIAGRAM

FIGURE 17-8:

TYPICAL I2C™

CONNECTIONS

The SSP module has six registers for I2C operation.

They are:

• SSP Control (SSPCON) register

• SSP Status (SSPSTAT) register

• Serial Receive/Transmit Buffer (SSPBUF) register

• SSP Shift Register (SSPSR), not directly

accessible

• SSP Address (SSPADD) register

• SSP Address Mask (SSPMSK) register

17.2.1

HARDWARE SETUP

Selection of I2C mode, with the SSPEN bit of the

SSPCON register set, forces the SCL and SDA pins to

be open drain, provided these pins are programmed as

inputs by setting the appropriate TRISC bits. The SSP

module will override the input state with the output data,

when required, such as for Acknowledge and slave-

transmitter sequences.

Read

Write

SSPSR Reg

Match Detect

SSPADD Reg

Start and

Stop bit Detect

SSPBUF Reg

Internal

Data Bus

Addr Match

SCL

SDA

Shift

Clock

MSb

LSb

SSPMSK Reg

Note:

Pull-up

resistors

must

provided

externally to the SCL and SDA pins for

proper operation of the I2C module.

Slave 1

Master

SDA

SCL

VDD

SDA

SCL

Slave 2

SDA

SCL

(optional)

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