PIC16F720-ESLASHML datasheet(146/244 Pages) MICROCHIP

146 / 244 page

PIC16F/LF720/721

DS41430A-page 146

 2010 Microchip Technology Inc.

SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit

= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

= A new byte is received while the SSPBUF register is still holding the previous data. In case of

overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode the overflow

bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF

= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

= Enables serial port and configures SCK, SDO and SDI as serial port pins(1)

= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

= Idle state for clock is a high level

= Idle state for clock is a low level

bit 3-0

SSPM<3:0>: Synchronous Serial Port mode Select bits

0000

= SPI Master mode, clock = FOSC/4

0001

= SPI Master mode, clock = FOSC/16

0010

= SPI Master mode, clock = FOSC/64

0011

= SPI Master mode, clock = TMR2 output/2

0100

= SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101

= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

Note 1:

When enabled, these pins must be properly configured as input or output.

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