PIC16F720-ESLASHML datasheet(123/244 Pages) MICROCHIP

123 / 244 page

 2010 Microchip Technology Inc.

DS41430A-page 123

PIC16F/LF720/721

16.1.2

AUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 16-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

bits of the character have been shifted in, they are

immediately transferred to a two character First-In

First-Out (FIFO) memory. The FIFO buffering allows

reception of two complete characters and the start of a

third character before software must start servicing the

AUSART receiver. The FIFO and RSR registers are not

directly accessible by software. Access to the received

data is via the RCREG register.

16.1.2.1

Enabling the Receiver

The AUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other AUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the AUSART. Clearing the SYNC bit

of the TXSTA register configures the AUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the AUSART and automatically

configures the RX/DT I/O pin as an input.

TABLE 16-1:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE

PEIE

TMR0IE

INTE

RABIE

TMR0IF

INTF

RABIF

0000 000x

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

SPBRG

BRG7

BRG6

BRG5

BRG4

BRG3

BRG2

BRG1

BRG0

0000 0000

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

1111 1111

TXREG

AUSART Transmit Data Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

Legend:

= unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous transmission.

Note:

When the SPEN bit is set, the TX/CK I/O

pin is automatically configured as an

output, regardless of the state of the

corresponding TRIS bit and whether or

not the AUSART transmitter is enabled.

The PORT latch is disconnected from the

output driver so it is not possible to use the

TX/CK pin as a general purpose output.

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