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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16F720-E/ML датащи(PDF) 119 Page - Microchip Technology |
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PIC16F720-E/ML датащи(HTML) 119 Page - Microchip Technology |
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119 / 244 page  2010 Microchip Technology Inc. DS41430A-page 119 PIC16F/LF720/721 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The AUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The AUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • Input buffer overrun error detection • Received character framing error detection • Half-duplex synchronous master • Half-duplex synchronous slave • Sleep operation Block diagrams of the AUSART transmitter and receiver are shown in Figure 16-1 and Figure 16-2. FIGURE 16-1: AUSART TRANSMIT BLOCK DIAGRAM TXIF TXIE Interrupt TXEN TX9D MSb LSb Data Bus TXREG Register Transmit Shift Register (TSR) (8) 0 TX9 TRMT SPEN TX/CK Pin Buffer and Control 8 SPBRG FOSC ÷ n n + 1 Multiplier x4 x16 x64 SYNC 100 BRGH x10 Baud Rate Generator •• • |
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